The week's pick
Reseach Article
Review Paper on Radix-2 DIT and DIF Fast Fourier Transform
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 151 - Number 6 |
| Year of Publication: 2016 |
| Authors: Kausar Ali, Nashrah Fatima, Paresh Rawat |
10.5120/ijca2016911848
|
Kausar Ali, Nashrah Fatima, Paresh Rawat . Review Paper on Radix-2 DIT and DIF Fast Fourier Transform. International Journal of Computer Applications. 151, 6 ( Oct 2016), 15-18. DOI=10.5120/ijca2016911848
Abstract
With the arrival of recent generation in the field of VLSI and communication, there is also an ever growing demand for low power consumption and minimum consumed chip area. It is also a well-known reality that the chip location and maximum combinational path delay (MCPD) unit forms an indispensable a part of processor layout. Due to this regard, high speed and low area architectures grow to be the want of the day. A fast Fourier transform (FFT) is any rapid algorithm for computing the DFT. The decimation-in-time (DIT) fast Fourier remodel (FFT) very often has advantage over the decimation-in-frequency (DIF) FFT for most real-valued programs, like speech/photo/video processing, biomedical sign processing, and time-collection evaluation, and so on., since it does now not require any output reordering.
References
- Charles. Roth Jr., “Digital Systems Design using VHDL”, Thomson Brooks/Cole, 7th reprint, 2005.
- S. S. Kerur, Prakash Narchi, Jayashree C N, Harish M Kittur and Girish V A, “Implementation of Vedic multiplier for Digital Signal Processing”, International Conference on VLSI, Communication & Instrumentation (ICVCI) 2011, Proceedings published by International Joural of Computer Applications® (IJCA), pp.1-6.
- Himanshu Thapaliyal and M.B Srinivas, “VLSI Implementation of RSA Encryption System Using Ancient Indian Vedic Mathematics”, Center for VLSI and Embedded System Technologies, International Institute of Information Technology Hyderabad, India.
- Jagadguru Swami Sri Bharati Krishna Tirthaji Maharaja, “Vedic Mathematics: Sixteen simple Mathematical Formulae from the Veda”, Delhi (2011).
- Harpreet Singh Dhillon and Abhijit Mitra, “A Reduced-bit Multiplication Algorithm for Digital Arithmetic”, International Journal of Computational and Mathematical Sciences, Febrauary 2008, pp.64-69.
- Sumit Vaidya and Depak Dandekar. “Delay-power performance comparison of multipliers in VLSI circuit design”. International Journal of Computer Networks & Communications (IJCNC), Vol.2, No.4, July 2010.
- Pramod Kumar Mehe, Basant Kumar Mohanty, Sujit Kumar Patel, Soumya Ganguly, and Thambipillai Srikanthan, “Efficient VLSI Architecture for Decimation-in-Time Fast Fourier Transform of Real-Valued Data”, IEEE Transactions on Circuits And Systems—I: Regular Papers, Vol. 62, No. 12, December 2015.
- M. Ayinala, Y. Lao, and K. K. Parhi, “An in-place FFT architecture for real-valued signals,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 60, no. 10, pp. 652–656, Oct. 2013.
- Shashank Mittal, Md. Zafar Ali Khan and M.B. Srinivas, “Area Efficient High Speed Architecture of Bruun’s FFT for Software Defined Radio”, 1930-529X/07/$25.00 © 2007 IEEE.
- B. G. Jo and M. H. Sunwoo, “New continuous-flow mixed-radix (CFMR) FFT processor using novel in-place strategy,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 5, pp. 911–919, May 2005.
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