CFP last date
22 April 2024
Reseach Article

A Novel Way to Design and Implement Statistical Operations based on FPGA

by Sarmad F. Ismael, Basil Shukr Mahmood
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 167 - Number 9
Year of Publication: 2017
Authors: Sarmad F. Ismael, Basil Shukr Mahmood
10.5120/ijca2017914359

Sarmad F. Ismael, Basil Shukr Mahmood . A Novel Way to Design and Implement Statistical Operations based on FPGA. International Journal of Computer Applications. 167, 9 ( Jun 2017), 8-11. DOI=10.5120/ijca2017914359

@article{ 10.5120/ijca2017914359,
author = { Sarmad F. Ismael, Basil Shukr Mahmood },
title = { A Novel Way to Design and Implement Statistical Operations based on FPGA },
journal = { International Journal of Computer Applications },
issue_date = { Jun 2017 },
volume = { 167 },
number = { 9 },
month = { Jun },
year = { 2017 },
issn = { 0975-8887 },
pages = { 8-11 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume167/number9/27798-2017914359/ },
doi = { 10.5120/ijca2017914359 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-07T00:14:22.905988+05:30
%A Sarmad F. Ismael
%A Basil Shukr Mahmood
%T A Novel Way to Design and Implement Statistical Operations based on FPGA
%J International Journal of Computer Applications
%@ 0975-8887
%V 167
%N 9
%P 8-11
%D 2017
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The architecture design for statistical operations to compute the Mean, Variance, Standard Deviation, RMS (Root Mean Square), Covariance, and MSE (Mean Square Error) values has been implemented on hardware concerning Xilinx Spartan 3E XC3S500E FPGA and worked properly up to maximum frequency of 73.252 MHz . The practical outcomes have been compared with the theoretical values calculated by Matlab with maximum error of 1.425%. New methods of design were concerned for the architecture of each function to reduce the number of slices.

References
  1. S. K Smith, United States of America: Newnes, 2003, ch.2 Digital Signal Processing.
  2. Sallee, Philip Andrew, 2004 Statistical methods for image and signal processing, PhD diss., UNIVERSITY OF CALIFORNIA DAVIS.
  3. D.B. Thomas and W. Lu, FPT 2008, Estimation of sample mean and variance for Monte-Carlo simulations. In ICECE Technology, International Conference on, pp. 89-96. IEEE.
  4. S. Sun and J. Zambreno, 2009 A Floating-point Accumulator for FPGA-based High Performance Computing Applications. IEEE International Conference in Field-Programmable Technology, Pages: 493 – 499.
  5. T. O. Bachir and J. P. David. 2010 performing floating-point accumulation on a modern FPGA in single and double precision. Field-Programmable Custom Computing Machines (FCCM), 18th IEEE Annual International Symposium on. IEEE.
  6. R. D. Mason, D. A. Lind and W. G. 1998 Marchal. Statistics: an introduction. Duxbury Pr.
  7. B.Jovanovic and M. Jevtic November 2010 FPGA Implementation of Throughput Increasing Techniques of The Binary Dividers, international scientific conference, Page: 397-401 19 – 20.
  8. T. Sutikno, A. Z. Jidin, A.Jidin and N. R. Idris, March 2012 Simplified VHDL Coding of Modified Non-Restoring Square Root Calculator , International Journal of Reconfigurable and Embedded Systems (IJRES), Vol. 1, No. 1,pages 37-42.
  9. D.Bishop, 1076-2008 Fixed point package user’s guide. Packages and bodies for the IEEE.
Index Terms

Computer Science
Information Sciences

Keywords

FPGA VHDL Statistical Operations Accumulators fixed point.