CFP last date
22 April 2024
Reseach Article

Low Power Wide Fan-in Control Pulse Operated Domino Multiplexor with Static Switching

by Vivek Mishra, Vivek Kumar Modanwal
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 172 - Number 8
Year of Publication: 2017
Authors: Vivek Mishra, Vivek Kumar Modanwal
10.5120/ijca2017915194

Vivek Mishra, Vivek Kumar Modanwal . Low Power Wide Fan-in Control Pulse Operated Domino Multiplexor with Static Switching. International Journal of Computer Applications. 172, 8 ( Aug 2017), 23-29. DOI=10.5120/ijca2017915194

@article{ 10.5120/ijca2017915194,
author = { Vivek Mishra, Vivek Kumar Modanwal },
title = { Low Power Wide Fan-in Control Pulse Operated Domino Multiplexor with Static Switching },
journal = { International Journal of Computer Applications },
issue_date = { Aug 2017 },
volume = { 172 },
number = { 8 },
month = { Aug },
year = { 2017 },
issn = { 0975-8887 },
pages = { 23-29 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume172/number8/28272-2017915194/ },
doi = { 10.5120/ijca2017915194 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-07T00:19:48.496325+05:30
%A Vivek Mishra
%A Vivek Kumar Modanwal
%T Low Power Wide Fan-in Control Pulse Operated Domino Multiplexor with Static Switching
%J International Journal of Computer Applications
%@ 0975-8887
%V 172
%N 8
%P 23-29
%D 2017
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In wide fan-in domino multiplexors, significant power losses are introduced due to the high switching activity at both dynamic and output nodes. In this paper a multiplexor is proposed with static switching at both dynamic and output nodes. This technique has a control pulse generator circuit which turns on the pull up transistor conditionally for a short duration only. This technique is advanced than previously existing techniques as it has faster response over other existing techniques but lesser power consumption and lesser area required. Simulation is done using 0.18µm CMOS technology. Power consumption of proposed multiplexor is calculated and the results are compared with existing multiplexors for different loading condition, clock frequency and temperature. For capacitance 100 fF, proposed domino multiplexor circuit reduces power consumption by 81.08%, 17.57% and 25.50% as compared to standard footless domino, SP-Domino and SSPD multiplexors.

References
  1. S. Wairya, R. K. Nagaria and S. Tiwari, ‘New design methodologies for high speed mixed-mode CMOS full adder circuits’, International Journal of VLSI design & Communication Systems (VLSICS), AIRCC Publication, 2011, 2, (2), pp.78-98.
  2. S.D. Naffziger, et al., ‘The implementation of the Itanium 2 microprocessor’, IEEE Journal of Solid-State Circuits, 2002, 37, pp.1448–1460.
  3. K. J. Nowka and T. Galambos, ‘Circuit design techniques for a gigahertz integer microprocessor’, IEEE International Conference on Computer Design, 1998, pp.11-16.
  4. Z. Liu and V. Kursun, ‘Leakage biased PMOS sleep switch dynamic circuits’, IEEE Transactions on Circuits and Systems,October 2006, 53, (10), pp.1093-1097.
  5. W.Hwang, R.V.Joshi, W.H.Henkels,‘A500-MHz, 32-word×64-bit, eight-port self-resetting CMOS register file’,IEEE Journal of Solid-State Circuits, 1999, 34, pp.56–67.
  6. R.K.Krishnamurthy, A.Alvandpour, G.Balamurugan, N.Shanbhag, K. Soumyanath, S.Y.Borkar, ‘A 130-nm 6-GHz 256×32 bit leakage-tolerant register file’,IEEE Journal of Solid-State Circuits, 2002, 37, pp. 624–632.
  7. H. Mahmoodi and K. Roy, ‘Diode-footed domino: A leakage-tolerant high fan-in dynamic circuits design style’, IEEE Transactions on Circuits and Systems,March 2004, 51, (3), pp.495-503.
  8. A. Amirabadi, A. A. Kusha, Y. Mortazavi and M. Nourani, ‘Clock delayed domino logic with efficient variable threshold voltage keeper’, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, February 2007, 15, (2), pp.125-134,.
  9. F. Tang and A. Bermak , ‘Low power TSPC-based domino logic circuit design with 2/3 clock load’,Transactionson Energy Procedia, 2012, 14, pp.1168-1174.
  10. Y. J. Ren. ,I. Karlsson and Svensson, ‘A true single-phase clock dynamic CMOS circuit technique’,IEEE Transactions on Solid-State Circuits, 1987, 22, pp.899-901.
  11. S. Jayakumaran, C. N. Hung, J. N. Kevin, K. Robert and B. Brown, ‘Controlled-load limited switch dynamic logic circuit’,IEEE Conference on Computer Society, 2005, pp.1-6.
  12. A. K. Pandey, R. A. Mishra and R. K. Nagaria, ‘Low power dynamic buffer circuits’,International Journal of VLSI design & Communication Systems (VLSICS), AIRCC Publication, 2012, 3, (5), pp.53-65.
  13. T. Fang, B. Amine and G. Zhouye , ‘Low power dynamic logic circuit design using a pseudo dynamic buffer’,Integration,the VLSI journal,201, 45, pp.395-404.
  14. J. A. Charbel and A. B. Magdy, ‘Single-phase SP –domino:A limited-switching dynamic circuit technique for low-power wide fan-in logic gates’,IEEE Transactions On Circuits and Systems, 2008, 55, pp.141-145.
  15. R. Singh, G. Moon, M. Kim, J. Park, W. Y. Shin and S. Kim, ‘Static-switching pulse domino:A switching-aware design technique for wide fan-in dynamic multiplexers’, Integratiom, The VLSI Journal,June 2012, 45, pp.253-262.
  16. Amit Kumar Pandey, Vivek Mishra, Ram Awadh Mishra, Rajendra Kumar Nagaria, V. Krishna Rao Kandanvli ‘Conditional Precharge Dynamic Buffer Circuit’ International Journal of Computer Applications, Vol.60, December 2012, pp.45-52.
  17. J. Wang, S. Shieh, C. Yeh, and Y. Yeh, ‘Pseudo-Footless CMOS Domino Logic Circuits for High-Performance VLSI Designs’, IEEE International Symposium on Circuits and Systems, 2004, 2, pp. 401-404.
  18. G. Wei and C. Sechen, ‘Clock-delayed domino for dynamic circuit design’, IEEE Transactions on Very Large Integration (VLSI) Systems,August 2000, 8, (4), pp.425-430.
Index Terms

Computer Science
Information Sciences

Keywords

Multiplexor Domino logic Dynamic circuits Low power Switching activity.