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A Novel Power Efficient Pre Encoded Modified Booth Multiplier Encoder

by Saumya Sharma, Bharti Gupta
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 175 - Number 4
Year of Publication: 2017
Authors: Saumya Sharma, Bharti Gupta
10.5120/ijca2017915515

Saumya Sharma, Bharti Gupta . A Novel Power Efficient Pre Encoded Modified Booth Multiplier Encoder. International Journal of Computer Applications. 175, 4 ( Oct 2017), 24-28. DOI=10.5120/ijca2017915515

@article{ 10.5120/ijca2017915515,
author = { Saumya Sharma, Bharti Gupta },
title = { A Novel Power Efficient Pre Encoded Modified Booth Multiplier Encoder },
journal = { International Journal of Computer Applications },
issue_date = { Oct 2017 },
volume = { 175 },
number = { 4 },
month = { Oct },
year = { 2017 },
issn = { 0975-8887 },
pages = { 24-28 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume175/number4/28477-2017915515/ },
doi = { 10.5120/ijca2017915515 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-07T00:24:10.672549+05:30
%A Saumya Sharma
%A Bharti Gupta
%T A Novel Power Efficient Pre Encoded Modified Booth Multiplier Encoder
%J International Journal of Computer Applications
%@ 0975-8887
%V 175
%N 4
%P 24-28
%D 2017
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The pre-encoded multipliers for encoding is quite useful for the digital signal processing in various applications of communication and data processing devices.The modified booth encoder proposed in this work is the technique to simplify the products implementation with the improvements in power consumption.The proposed architecture has less power than previous architecture. The synthesis results show the power required for proposed architecture is 14mW only. This will work longer on the same power as given to previous design.

References
  1. Small area modified booth multiplier design for predetermined coeffi¬cients," IEICE Trans. Fundam. Electron. Commun. Comput. Sci., vol. E90-A, no. 3, pp. 694-697, Mar. 2007.
  2. K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation. John Wiley & Sons, 2007
  3. B. C. Paul, S. Fujita and M. Okajima, "ROM-Based Logic (RBL) Design: A Low-Power 16 Bit Multiplier," in IEEE Journal of Solid-State Circuits, vol. 44, no. 11, pp. 2935-2942, Nov. 2009.
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  5. N. G. NikDaud, F. R. Hashim, M. Mustapha and M. S. Badruddin, "Hybrid modified booth encoded algorithm-carry save adder fast multiplier," The 5th International Conference on Information and Communication Technology for The Muslim World (ICT4M), Kuching, 2014, pp. 1-6.
  6. B. Dinesh, V. Venkateshwaran, P. Kavinmalar and M. Kathirvelu, "Comparison of regular and tree based multiplier architectures with modified booth encoding for 4 bits on layout level using 45nm technology," 2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE), Coimbatore, 2014, pp. 1-6.
  7. K. Tsoumanis, N. Axelos, N. Moschopoulos, G. Zervakis and K. Pekmestzi, "Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding," in IEEE Transactions on Computers, vol. 65, no. 2, pp. 670-676, Feb. 1 2016.
Index Terms

Computer Science
Information Sciences

Keywords

Pre-encoded Booth Multiplier Encoder

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