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Microprocessor Compatible PWM Generator Implement on FPGA

by Bapan Singh, Prashant Kumar Dubey, Arijit Roy, Debarshi Datta
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 180 - Number 7
Year of Publication: 2017
Authors: Bapan Singh, Prashant Kumar Dubey, Arijit Roy, Debarshi Datta
10.5120/ijca2017916065

Bapan Singh, Prashant Kumar Dubey, Arijit Roy, Debarshi Datta . Microprocessor Compatible PWM Generator Implement on FPGA. International Journal of Computer Applications. 180, 7 ( Dec 2017), 43-45. DOI=10.5120/ijca2017916065

@article{ 10.5120/ijca2017916065,
author = { Bapan Singh, Prashant Kumar Dubey, Arijit Roy, Debarshi Datta },
title = { Microprocessor Compatible PWM Generator Implement on FPGA },
journal = { International Journal of Computer Applications },
issue_date = { Dec 2017 },
volume = { 180 },
number = { 7 },
month = { Dec },
year = { 2017 },
issn = { 0975-8887 },
pages = { 43-45 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume180/number7/28815-2017916065/ },
doi = { 10.5120/ijca2017916065 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-07T01:00:02.414667+05:30
%A Bapan Singh
%A Prashant Kumar Dubey
%A Arijit Roy
%A Debarshi Datta
%T Microprocessor Compatible PWM Generator Implement on FPGA
%J International Journal of Computer Applications
%@ 0975-8887
%V 180
%N 7
%P 43-45
%D 2017
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper is concerned about microprocessor compatible PWM generator architecture by using Field Programmable Gate Array (FPGA). In PWM the variation of duty cycle change the width of the pulse. The PWM generator (PWMG) is interfaced to the bus of a microprocessor. The microprocessor initiates PWMG to specify duty cycle. The duty cycle remain unchanged until new data available to the PWMG from microprocessor unit. The output signal of PWMG is logic “1” and logic “0” for a specific time period. The architecture has been designed with VHDL code and verified using Xilinx ISE Design Suite 14.7. The design is successfully implemented on SPRATAN-6 FPGA board. The operating frequency of this proposed architecture is of 292.650MHz.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Duty cycle Microprocessor PWM VHDL FPGA