UNITED STATES
High Throughput Multipliers Using Delay Equalization
|
10.5120/661-929 |
Alka Raj and N.Kayalvizhi. Article: High Throughput Multipliers Using Delay Equalization. International Journal of Computer Applications 2(4):9–13, June 2010. Published By Foundation of Computer Science. BibTeX
@article{key:article,
author = {Alka Raj and N.Kayalvizhi},
title = {Article: High Throughput Multipliers Using Delay Equalization},
journal = {International Journal of Computer Applications},
year = {2010},
volume = {2},
number = {4},
pages = {9--13},
month = {June},
note = {Published By Foundation of Computer Science}
}
Abstract
Pipelining is used for increasing the throughput of the system. Wave pipelining is done by removing the intermediate registers present in the pipelined circuits so that there will be only an input register and an output register. Circuit should be modelled in such a way that all data from one stage should reach the next stage at the same time so that overlapping of data will not occur. In wave pipelined system the clock period should be greater than the difference between maximum delay and minimum delay + clocking overheads such as setup time, hold time, etc. Clock period can be reduced by minimizing the difference between maximum and minimum delay, i.e delay equalization has to be done. Delay equalization can be done by logic restructuring combined with Wong’s algorithm and Klass’s algorithm. Area can be further decreased by using delay element shifting and delay element sharing.
Reference
-
G.Lakshminarayanan,B.Venkataramani, “Optimization techniques for FPGA based wave-pipelined DSP blocks”, in Proc IEEE Transactions on VLSI Systems,vol.13,number7,pp.783-793,July 2005 .
K. K. Parhi, VLSI Signal Processing Systems. New York: Wiley, 1999.
W. P. Burleson, M. Ciesielski, F. Klass, and F. Liu, “Wave-pipelining: a tutorial and research survey” in IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 6, no. 3, pp. 464–474, Sep. 1998.
D.C Wong,G. DeMicheli,and M.J Flynn, “Designing High-Performance Digital Circuits Using Wave Pipelining: Algorithms and Practical Experiences”, in IEEE Trans Comput Aided Des Integr . circuits syst.,vol. 12, no. 1, pp 25-46, Jan 1993.
Rui Tang,Yong-Bin Kim, “A novel delay balancing methodology for wave pipelined circuits”, 48th midwest symposium on Circuit and systems, pp. 1035-1038, vol 2 ,Aug 2005 IEEE
E.I.Boemo, S.Lopez-Buedo, J.M.Meneses, “Wave pipelining via look-up tables” in Proc IEEE Int.Symp.circuits systems,vol 4,1996, pp185-1884.
Srivastav Sethupathy,Nohpill Park,Marcin Paprzycki , “Logic restructuring for delay balancing in wave-pipelined circuits: an integer programming approach”, in proceedings of the seventh international symposium on symbolic and numeric algorithms for scientific computing,2005 IEEE.
| < Prev | Next > |
|---|
