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Built-In Self-Repair for multiple RAMs with different Redundancies in a SOC

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International Journal of Computer Applications
© 2011 by IJCA Journal
Number 1 - Article 1
Year of Publication: 2011
Authors:
Shekar Babu M
Sumanth Kumar Reddy
S V V Sateesh
10.5120/2971-3995

Shekar Babu M, Sumanth Kumar Reddy and S V V Sateesh. Article: Built-In Self-Repair for Multiple RAMs with Different Redundancies in a SOC. International Journal of Computer Applications 24(8):26–29, June 2011. Published by Foundation of Computer Science. BibTeX

@article{key:article,
	author = {Shekar Babu M and Sumanth Kumar Reddy and S V V Sateesh},
	title = {Article: Built-In Self-Repair for Multiple RAMs with Different Redundancies in a SOC},
	journal = {International Journal of Computer Applications},
	year = {2011},
	volume = {24},
	number = {8},
	pages = {26--29},
	month = {June},
	note = {Published by Foundation of Computer Science}
}

Abstract

As RAM is major component in present day SOC, by improving the yield of RAM improves the yield of SOC. So the repairable memories play a vital role in improving the yield of chip. This paper presents the efficient Reconfigurable Built-in Self Repair (Re BISR) circuit along with 2D redundancies (spare row/column) and spare cells. Since most of faults are single cell fault, the area of spare is effectively utilized by replacing defected cell with spare cell. This in turn increases repair rate. The proposed repair circuit is Reconfigurable for less area, used to repair multiple memories with different in size and redundancy. The experimental results show that proposed ReBISR circuit reduces the area and increases the yield of the memory.

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