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Technique for Template Generation for Simultaneous Testing of Multiple Identical Functional Units in Super-scalar Architecture
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 34 - Number 8 |
| Year of Publication: 2011 |
| Authors: Rahul Raj Choudhary, Gayaprasad Sinsinwar, Aditi Kajala, Pooja Bhardwaj |
10.5120/4122-5843
|
Rahul Raj Choudhary, Gayaprasad Sinsinwar, Aditi Kajala, Pooja Bhardwaj . Technique for Template Generation for Simultaneous Testing of Multiple Identical Functional Units in Super-scalar Architecture. International Journal of Computer Applications. 34, 8 ( November 2011), 37-41. DOI=10.5120/4122-5843
Abstract
At-speed testing has emerged as dominant test requirement in the era of high speed microprocessors. Since the conventional testing techniques prove to be incompetent, Instruction-Based Self-Testing (IBST) has been proposed as an effective alternate to those conventional techniques for at-speed testing of high performance microprocessors. The Superscalar architectures, with vast functionality and exceptionally high speed have become the central integral part of modern high speed digital systems. However, testing superscalar microprocessors using this approach faces serious challenges, due to the out-of-order execution with multiple functional units and in-order commit behaviour. This paper discusses the test program generation procedure (template based) for multiple identical functional units in a superscalar architecture. Procedures for delay fault testing, which make sure that generated test vectors are applied in the correct order to test each testable path, are developed. The preliminary work has been presented in EWDTS[1]
References
- Gayaprasad Sinsinwar, Rahul Raj Choudhary, Aditi Kajala, Virendra Singh,“Test Program Generation for Simultaneous Testing of Multiple Identical Functional Units in Super-scalar Architecture”, IEEE East-West Design and Test Symposium (EWDTS) 2010, St. Petersburg, Russia, Sep 2010, pp. 195-199.
- Aditi Kajala, Gayaprasad Sinsinwar, Rahul Raj Choudhary, Jaynarayan Tudu, Virendra Singh, “On Selection of State Variables for Delay Test of Identical Functional Units”, IEEE East-West Design and Test Symposium (EWDTS) 2010, St. Petersburg, Russia, Sep 2010, pp. 200-203.
- S.M. Thatte and J. Abraham, “Test generation for Microprocessors”, IEEE Trans. on Computers, Vol. C-29, No. 6, June 1980, pp. 429-441.
- J. Shen and J.A. Abraham, “Native Mode Functional Test Generation for Processors with Applications to Self-Test and Design Validation”, Proc. of the International Test Conference 1998, pp. 990-999.
- K. Batcher and C. Papachristou, “Instruction Randomization Self Test for Processor Cores” Proc. of the VLSI Test Symposium 1999, pp. 34-40.
- L. Chen, and S. Dey, “Software-Based Self-Testing Methodology for Processor Cores”, IEEE Trans. on CAD of Integrated Circuits and Systems, Vol. 20, No.3, March 2001, pp. 369-380.
- N. Krantis, A. Paschalis, D. Gizopoulos, and Y. Zorian, “Instruction-Based Self-Testing of Processor Cores”, Journal of Electronic Testing: Theory and Application (JETTA) 19, 2003, pp 103-112.
- K.Kambe, M.Inoue, and H. Fujiwara, “Efficient Template Generation for Instruction-Based Self-Test of Processor Cores”, Proc. of Asian Test Symposium, 2004, pp. 152-157.
- L. Chen, S. Ravi, A. Raghunath, and S. Dey, “A Scalable Software-Based Self-Test Methodology for Programmable Processors”, Proc. of Design Automation Conference 2003, pp. 548-553.
- N.Krantis, G.Xenoulis, A.Paschalis, D.Gizopolous, and Y.Zorian, “Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores”, Proc. of International Test Conference, 2003, pp 431-440.
- Paschalis, and D. Gizopoulos, “ Effective Software-Based Self-Test Strategies for On-Line periodic Testing of Embedded Processors”, Proc. of Design and Test in Europe 2004, pp 578-583.
- W.-C. Lai, A. Krstic, and K.-T. Cheng, “On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set”, Proc. of the VLSI Test Symposium 2000, pp. 15-20.
- W.-C. Lai, A. Krstic, and K.-T. Cheng, “Test Program Synthesis for Path Delay Faults in Microprocessor Cores”, Proc. of International Test Conference 2000, pp 1080-1089.
- W.-C. Lai, and K.-T. Cheng, “Instruction-Level DFT for Testing Processor and IP Cores in System-on-a-Chip”, Proc. of the Design Automation Conference 2001, ACM Press, NY, 2001, pp. 59-64.
- V. Singh, M. Inoue, K.K. Saluja, and H. Fujiwara, “Instruction-Based Delay Fault Testing of Processor Cores”, Proc. of the International Conference on VLSI Design 2004, pp 933-938.
- V. Singh, M. Inoue, K.K. Saluja, and H. Fujiwara, “Delay Fault Testing of Processor Cores in Functional Mode”, IEICE Trans. on Information & Systems, Vol. E-88D, No. 3, March 2005, pp. 1-9.
- V. Singh, M. Inoue, K.K. Saluja, and H. Fujiwara, “Instruction-Based Delay Fault Testing of Pipelined Processor Cores”, Proc. of International Symposium on Circuits and Systems 2005.
- V.Singh, M.Inoue, K.K.Saluja, and H.Fujiwara, “Program Based Self-Testing of Superscalar Microprocessors”, Proc. of North Atlantic Test Workshop (NATW), 2005. 19. Krstic and K.-T. Cheng, Delay fault testing for VLSI circuits, Kluwer Academic Publishers, 1998.
- M. Hatzimihail et al., A Methodology for Detecting performance Faults in Microprocessor Speculative Execution Units via Hardware Performance Monitoring”, in Proc. of International Test Conference
- ITC, 2007.
- G. Theodorou et al., “A Software Based Self-Test Methodology for In-System Testing of Processor Cache tag Arrays”, in Proc. of International On-Line Testing Symposium (IOLTS) 2010
- Pomeranz and S.M. Reddy, “Selecting State Variables for Improved On-line Testability Through Output Response Comparison of Identical Circuits”, in Proc. of International On-Line Testing Symposium (IOLTS) 2010.
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