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A Technique to Reduce Glitch Power during Physical Design Stage for Low Power and Less IR Drop
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 39 - Number 18 |
| Year of Publication: 2012 |
| Authors: Vasantha Kumar B.V.P, N. S. Murthy Sharma, K. Lal Kishore |
10.5120/5086-7450
|
Vasantha Kumar B.V.P, N. S. Murthy Sharma, K. Lal Kishore . A Technique to Reduce Glitch Power during Physical Design Stage for Low Power and Less IR Drop. International Journal of Computer Applications. 39, 18 ( February 2012), 62-67. DOI=10.5120/5086-7450
Abstract
A glitch compensation methodology is proposed in this paper which involves in reducing the undesired switching of combinational circuits in order to save dynamic power. The proposed methodology can be seamlessly integrated to existing physical design flow to reduce the glitch power which is one of the major contributing factors for both dynamic and IR drop. A glitch is an undesired transition that occurs before intended value in digital circuits. A glitch occurs in CMOS circuits when differential delay at the inputs of a gate is greater than inertial delay, which results into notable amount of power consumption. The glitch power is becoming more prominent in lower technology nodes. Introduction of buffers at the input of the Logic gate may reduce glitches, but it results into large area overhead and dynamic power. Hence, the proposed methodology will ensure low dynamic power consumption with less area. The pass transistor logic is used as a compensation circuit and a flow is also proposed for characterizing the pass transistor logic to cater different delay values. The proposed methodology has been validated using Synopsys 90nm SAED PDK.
References
- A..Shen,A.Ghosh,S.Devadas and K.Keutzer, “On average power dissipation and random pattern testability of CMOS combinational logic networks,”proc. ICCAD,pp.402-407,1992.
- D.Brad and C.Vishweshwaraiah, “Inaccuracies in power estimation during logic synthesis,” proc. ICCAD,pp.388-394,1996.
- M. T. Bohr, R. S. Chau, T. Ghani, and K. Mistry, “The high-k solution,” IEEE Spectrum, vol. 44, no. 10, pp. 29–35, Oct. 2007.
- W. C. Elmore, “The transient response of damped linear networks with particular regard to wide-band amplifiers,” J. Appl. Phys., vol. 19, no. 1, pp. 55–63, Jan. 1948.
- J. Rabaey, A. Chandrakasan, and B. Nikolic´, Digital Integrated Circuits:A Design Perspective. Upper Saddle River, NJ: Prentice-Hall, 2003.
- N. H. E.Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, third ed. Boston, MA: Pearson Addison-Wesley, 2005.
- T.Raja, V.D.Agarwal “Variable input delay CMOS logic for low power design”, IEEE Trans. Circuits syst.,vol.-17,no.10,October 2009.
- Low-Power CMOS Design, A. Chandrakasan and R. Brodersen, Eds. Piscataway, NJ: IEEE Press, 1998.
- A. P. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design. Boston, MA: Springer, 1995.
- P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low power CMOS digital design,” IEEE J. Solid-State Circuits, vol. 27, no. 4, pp. 473–484, Apr. 1992.
- J. M. Rabaey and M. Pedram, Low Power Design Methodologies. Boston, MA: Kluwer, 1996.
- K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit Design. New York: Wiley, 2000.
- V. D. Agrawal, “Low power design by hazard filtering,” in Proc. 10th Int. Conf. VLSI Des., Jan. 1997, pp. 193–197.
- M. Berkelaar, “Statistical delay calculation,” in Proc. Workshop Notes Int. Workshop Logic Synth., Lake Tahoe, CA, May 1997, pp. 2.1.1–2.1.4.
- M. Berkelaar, “Statistical delay calculation: A linear time method,” in Proc. IEEE Int.Workshop Timing Issues Specif. Synth. Digit. Syst., Dec. 1997, pp. 15–24.
- M. Berkelaar, P. Buurman, and J. Jess, “Computing entire area/power consumption versus delay trade-off curve for gate sizing using a piecewise linear simulator,” IEEE Trans. Circuits Syst., vol. 15, no. 11, pp. 1424–1434, Nov. 1996.
- M. Berkelaar and E. Jacobs, “Using gate sizing to reduce glitch power,”in Proc. ProRISC Workshop Circuits, Syst., Signal Process., Mierlo, The Netherlands, Nov. 1996, pp. 183–188.
- M. Berkelaar and E. T. A. F. Jacobs, “Gate sizing using a statistical delay model,” in Proc. Des. Autom. Test Eur. Conf., Paris, France, Mar. 2000, pp. 283–290.
- M. Berkelaar and J. A. G. Jess, “Transistor sizing in MOS digital circuits with linear programming,” in Proc. Eur. Des. Autom. Conf., Mierlo, The Netherlands, Mar. 1990, pp. 217–221.
- S. Datta, S. Nag, and K. Roy, “ASAP: A transistor sizing tool for area,delay and power optimization of CMOS circuits,” in Proc. IEEE Int.Symp. Circuits Syst., May 1994, pp. 61–64.
- J. P. Fishburn and A. E. Dunlop, “TILOS: A posynomial approach to transistor sizing,” in Proc. Int. Conf. Comput.-Aided Des., Nov. 1985, pp. 326–328.
- C. V. Schimpfle, A. Wroblewski, and J. A. Nassek, “Transistor sizing for switching activity reduction in digital circuits,” in Proc. Eur. Conf. Circuit Theory Des., Aug. 1999, vol. 1, pp. 114–117.
- V. Sundararajan, S. Sapatnekar, and K. Parhi, “Fast and exact transistor sizing based on iterative relaxation,” IEEE Trans. Comput.-Aided Des. Circuits Syst., vol. 21, no. 5, pp. 568–581, May 2002.
- A. Wroblewski, C. V. Schimpfle, and J. A. Nassek, “Automated transistor sizing algorithm for minimizing spurious switching activities in CMOS circuits,” in Proc. IEEE Int. Symp. Circuits Syst., May 2000, pp. 291–294.
- A. Wroblewski, O. Schumacher, C. V. Schimpfle, and J. A. Nassek, “Minimizing gate capacitances with transistor sizing,” in Proc. IEEE Int Symp. Circuits Syst., May 2001, pp. 186–189
- V. D. Agrawal, M. L. Bushnell, G. Parthasarathy, and R. Ramadoss, “Digital circuit design for minimum transient energy and a linear programming method,” in Proc. 12th Int. Conf. VLSI Des., Jan. 1999, pp. 434–439.
- T. Raja, “A reduced constraint set linear program for low-power design of digital circuits,”M.S. thesis, Dept. ECE, Rutgers Univ., Piscataway, NJ, 2002.
- T. Raja, V. D. Agrawal, and M. L. Bushnell, “Minimum dynamic power CMOS circuit design by a reduced constraint set linear program,” in Proc. 16th Int. Conf. VLSI Des., Jan. 2003, pp. 527–532.
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