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10.5120/815-1156 |
P K Singh and Rajendra Kumar. Article: Role of Multiblocks in Control Flow Prediction using Parallel Register Sharing Architecture. International Journal of Computer Applications 4(4):29–32, July 2010. Published By Foundation of Computer Science. BibTeX
@article{key:article,
author = {P K Singh and Rajendra Kumar},
title = {Article: Role of Multiblocks in Control Flow Prediction using Parallel Register Sharing Architecture},
journal = {International Journal of Computer Applications},
year = {2010},
volume = {4},
number = {4},
pages = {29--32},
month = {July},
note = {Published By Foundation of Computer Science}
}
Abstract
In this paper we present control flow prediction (CFP) in parallel register sharing architecture to achieve high degree of ILP. The main idea behind this concept is to use a step beyond the prediction of common branch and permitting the architecture to have the information about the CFG (Control Flow Graph) components of the program to have better branch decision for ILP. The navigation bandwidth of prediction mechanism depends upon the degree of ILP. It can be increased by increasing control flow prediction at compile time. By this the size of initiation is increased that allows the overlapped execution of multiple independent flow of control. The multiple branch instruction can also be allowed. These are intermediate steps to be taken in order to increase the size of dynamic window to achieve a high degree of instruction level parallelism exploitation.
Reference
-
Eduardo Qui˜nones, Joan-Manuel Parcerisa, “Improving Branch Prediction and Predicated Execution in Out-of-Order Processors” Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture, pp: 75-84, 2007.
David I. August, Wen-Mei W. Hwu, Scott A. Mahlke, “The Partial Reverse If-Conversion Framework for Balancing Control Flow and Prediction”, International Journal of Parallel Programming Volume 27, Issue 5, pp. 381– 423, 1999.
Dionisios N. Pnevmatikatos, Manoj Franklin, Gurindar S. Sohi, “Control flow prediction for dynamic ILP processors”, International Symposium on Microarchitectur, Proceedings of the 26th annual international symposium on Microarchitecture, pp. 153 – 163, 1993.
Guilin Chen, Mahmut Kandemir, “Compiler-Directed Code Restructuring for Improving Performance of MPSoCs”, IEEE Transactions on Parallel and Distributed Systems, Volume 19, No. 9, 2008.
J Cong, Guoling Han, Zhiru Zhang, “Architecture & compilation for data bandwidth improvement in configurable embedded processors”, International Conference on Computer Aided Design Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, pp. 263-270. 2005.
J. Fisher, “Trace Scheduling: A Technique for Global Microcode Compaction”, IEEE Transactions on Computers, vol. C-30, July 1981.
J. K. F. Lee and A. J. Smith, “Branch Prediction Strategies and Branch Target Buffer Design”, IEEE Computer, Volume 17, pp. 6-22, 1984.
Lam Wilson, “Limits of control flow on parallelism”, Proceedings of 19th annual International symposium on Computer Architecture, pp. 46-57, 1992.
P. Chang, S. Mahlke, W. Chen, N. Warter, W. Hwu, “IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors”, Proceeding 18th Annual International Symposium on Computer Architecture, May 1991.
P. Y. T. Hsu and E. S. Davidson, “Highly Concurrent Scalar Processing”, Proceeding 13th Annual International Symposium on Computer Architecture, June 1986.
R. Colwell, R. Nix, J. O’Donnell, D. Papworth, and P. Rodman, “A VLIW Architecture for a Trace Scheduling Compiler”, IEEE Transactions on Computers, Volume 37, pp. 967-979, 1988.
Rajendra Kumar, P K Singh, “A Modern Parallel Register Sharing Architecture for Code Compilation”, IJCA, Volume 1, No. 16, pp. 108-113, 2010.
S. Mahlke, D. Lin, W. Chen, R. Hank, and R. Bringmann, ‘‘Effective Compiler Support for Predicated Execution Using the Hyperblock”, Proceedings of the 25th Annual Workshop on Microprogramming and Microarchitecture, 1992.
S. T. Pan, K. So, and J. T. Rahmeh, “Improving the Accuracy of Dynamic Branch Prediction Using Branch Correlation”, Proceeding Architectural Support for Programming Languages and Operating Systems (ASPLOS-V), 1992.
Steve Carr, “Combining Optimization for Cache and Instruction-Level Parallelism”, Proceedings of the 1996 Conference on Parallel Architectures and Compilation Techniques, 1996.
T. Yeh and Y. Patt, “A Comparison of Dynamic Branch Predictors that use Two Levels of Branch History”, Proceeding 20th Annual International Symposium on Computer Architecture, May 1993.
Vijay S. Pai, Parthasarathy Ranganathan, Hazim Abdel-Shafi, Sarita Adve, “The Impact of Exploiting Instruction-Level Parallelism on Shared-Memory Multiprocessors”, IEEE Transactions on Computers, Volume 48 , Issue 2, Special issue on cache memory and related problems, pp. 218 – 226, 1999.
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