This paper presents the analysis of iterative decoder in terms of clock frequency/speed. Iterative decoding is a powerful technique for error correction in communication system. Low Density Parity Check Codes (LDPC), due to their near Shannon limit performance under iterative decoding has significant attention in real life communication applications. In the literature, various algorithms of iterative decoder have been addressed with trade off of computational complexity and decoding performance. Min-Sum (MS) algorithm, with reduced computational complexity is taken into the consideration. The architecture of MS decoder is designed at the transistor level transistor level targeted to 45 nm technology. The designed architecture is optimized using Wave pipelining, specifically buffer insertion. Timing optimization is done with the proper placement of buffer, at the various paths of the architecture. Wave pipelining is a method of high performance circuit design which implements pipelining in logic without the use of intermediate latches or registers. The maximum and minimum delay path is analyzed in the architecture. The performance metrics such as the clock frequency, power and delay are analyzed. The optimized architecture operates at a better speed with marginal increase in power.

Vlsi Buffer Insertion Wave Pipelining Clock Frequency Ldpc Codes Min-sum Algorithm