The week's pick
Reseach Article
LPSR: Novel Low Power State Retention Technique for CMOS VLSI Design
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 51 - Number 18 |
| Year of Publication: 2012 |
| Authors: Rajani H.p., S. Y. Kulkarni |
10.5120/8145-1931
|
Rajani H.p., S. Y. Kulkarni . LPSR: Novel Low Power State Retention Technique for CMOS VLSI Design. International Journal of Computer Applications. 51, 18 ( August 2012), 42-49. DOI=10.5120/8145-1931
Abstract
In mobile computing and mobile communication applications powered by battery, the battery life is a premier concern. Leakage power loss is critical in CMOS VLSI circuits as it leaks the battery even when devices are in idle state. To reduce subthreshold leakage power as well as total power in CMOS logic gates and circuits a new circuit technique called LPSR Technique is proposed in this work. Earlier well known techniques for leakage reduction and state retention are compared with this technique. This technique reduces maximum amount of leakage power during deep sleep mode, maximum power reduction during dynamic (clocked) mode and has a provision of preserving state in low power sleep mode. All the circuits are designed, simulated and low power performance evaluation is done using 90nm CMOS technology files in Cadence Design Environment.
References
- Y. Taur, A. Chandrakasan, W. J. Bowhill, and F. Fox, Eds. Piscataway, "CMOS scaling and issues in sub-0. 25 ?m systems in Design of High-Performance Microprocessor Circuits," NJ: IEEE, 2001, pp. 27–45.
- Kaushik Roy, Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, "Leakage Current Mechanisms and Leakage Reduction Techniques in Deep Submicrometer CMOS Circuits," Proceedings of the IEEE, vol. 91, No. 2, February 2003.
- Neil Weste, David Harris Ayan Banerjee, CMOS VLSI Design: A Circuits and Systems Perspective, III Edition, Pearson Education.
- S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, "1-V power supply high-speed digital circuit technology with multi-threshold voltage CMOS," IEEE J. Solid-State Circuits, vol. 30, pp. 847–854, Aug. 1995.
- L. Wei, Z. Chen, M. Johnson, K. Roy, Y. Ye, and V. De, "Design and optimization of dual threshold circuits for low voltage low power applications," IEEE Trans. VLSI Systems, pp. 16–24, Mar. 1999.
- Amit Agarwal, Hai Li, and Kaushik Roy,"DRG –Cache: A data retention gated ground cache for low power," Proceedings of the 39th Design Automation Conference, June 2002.
- Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, and Kevin Stawiasz ,"Experimental Measurement of A Novel Power Gating Structure with Intermediate Power saving mode", Proceedings of the 2004 International Symposium on Low Power Electronics and Design (ISLPED).
- S. H. Kim and V. J. Mooney, "Sleepy keeper: a new approach to low leakage power VLSI design," VLSI-SoC 2006
- Lakshminathan, P. and Nunez," VCLEARIT: A VLSI CMOS :Circuit Leakage Reduction Technique for Nanoscale Technologies," Proceedings of the Advanced Low Power Systems Workshop, at the 21st ACM International Conference on Supercomputing (June 2007), pp. 15-22
- N. Hanchate and N. Ranganathan, "Lector: A technique for leakage reduction in CMOS circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 2, pp. 196-205, February 2004.
- Srikanth Katrue and Dhireesha Kudithipudi,"GALEOR: Leakage reduction for CMOS circuits," 15th IEEE International Conference on Electronics, Circuits and Systems, pp. 574-577, Aug. 2008.
- M. Geetha Priya, K. Baskaran and D. Krishnaveni, "A Novel Leakage Power Reduction technique for CMOS VLSI Circuits", European Journal of Scientific Research, ISSN 1450-216X Vol. 74 No. 1 (2012), pp. 96-105.
- Rajani H. P. , Hansraj Guhilot and S. Y. Kulkarni, "Novel Stable SRAM for Ultra Low Power Deep Submicron Cache Memories", IEEE Recent Advances in Intelligent Computational Systems, RAICS 2011, in IEEE Explorer.
- Rajani H. P. and Srimannarayana Kulkarni, "Novel Sleep Transistor Techniques for Low Leakage Power in Peripheral Circuits,"International Journal of VLSI and Communication Systems, in Press.
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