CFP last date
20 May 2024
Call for Paper
June Edition
IJCA solicits high quality original research papers for the upcoming June edition of the journal. The last date of research paper submission is 20 May 2024

Submit your paper
Know more
The week's pick
Responsive image
Enhancing Privacy Preservation: Multi-Attribute Protection with P-Sensitive K-Anonymity

Twinkle Patel Kiran Amin
Random Articles
Reseach Article

Different Parameter Analysis of CMOS Charge Sharing Latch Comparator using 90nm Technology

by Ajay Vishwakarma, Sweta Sahu, Vijay Vishwakarma, Richa Soni
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 63 - Number 11
Year of Publication: 2013
Authors: Ajay Vishwakarma, Sweta Sahu, Vijay Vishwakarma, Richa Soni
10.5120/10507-5381

Ajay Vishwakarma, Sweta Sahu, Vijay Vishwakarma, Richa Soni . Different Parameter Analysis of CMOS Charge Sharing Latch Comparator using 90nm Technology. International Journal of Computer Applications. 63, 11 ( February 2013), 1-6. DOI=10.5120/10507-5381

@article{ 10.5120/10507-5381,
author = { Ajay Vishwakarma, Sweta Sahu, Vijay Vishwakarma, Richa Soni },
title = { Different Parameter Analysis of CMOS Charge Sharing Latch Comparator using 90nm Technology },
journal = { International Journal of Computer Applications },
issue_date = { February 2013 },
volume = { 63 },
number = { 11 },
month = { February },
year = { 2013 },
issn = { 0975-8887 },
pages = { 1-6 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume63/number11/10507-5381/ },
doi = { 10.5120/10507-5381 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:15:09.891780+05:30
%A Ajay Vishwakarma
%A Sweta Sahu
%A Vijay Vishwakarma
%A Richa Soni
%T Different Parameter Analysis of CMOS Charge Sharing Latch Comparator using 90nm Technology
%J International Journal of Computer Applications
%@ 0975-8887
%V 63
%N 11
%P 1-6
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In the present works, mainly power consumption of circuit is main issue for every designers. This paper mainly dealing with the implementation of CMOS Charge sharing latch Comparator and analysis of it using different parameter in 90nm. For the implementation of new design the features of two important Comparator are combined so that the power dissipation is reduced and speed of new design is increased. These two Comparator are Resistive Dividing Comparator and Differential Current sensing respectively. The simulation result is shown in 90nm technologies, for 2. 4GHz clocked comparator by using 0. 9V input. Again the result of 90nm technology is compared with 180nm technology to show the reduction of power and enhancement of speed. The implementation is done on the Cadence virtuoso design environment.

References
  1. R. Wang, Kaihang Li, J. Zhang, Bin Nie, " A High Speed High Resolution Latch Comparator for pipeline ADC", pp 28-31, IEEE, 2007.
  2. S . Sheikaei, S. Mirabbasi, and A. Ivanov, "A 0. 35µm CMOS Comparator Circuit For High-Speed ADC Applications", pp 6134-6137, IEEE, 2007.
  3. Khosrov Dabbagh Sadeghipour," Resolution Enhanced latch Comparator", pp 29-35, IEEE ,2001.
  4. Meghana Kulkarni, V. Sridhar , G. H. Kulkarni,"The Quantized Differential Comparator in Flash Analog to Digital C design" Vol. 2, No. 4, july 2010, IJCNC.
  5. Hao Gao, Peter Baltus and Qiao Meng," Low voltage comparator for High Speed ADC", ISSSE 2010.
  6. P. Uthaichana and E. Leelarasmee, "Low power CMOS Dynamic Latch Comparators,"IEEE, pp. 605-608, 2003.
  7. Z . Huang and P. Zhong," An Adaptive Analog –to-Digital Converter Based on Low-Power Dynamic latchcomparator," IEEE Conference , p. 6pp, 2005.
  8. Soheli Farhan, A. H. M. Zahirul Alam, Sheroz Khan, Md. Ataur Rahman," Design of a Comparator for Quaternary Multi Valued Analog to Digital Converter," IEEE 2011.
  9. HeungJun Jeon, Yong-Bin Kim and Minsu Choi,"Offset Voltage Analysis of Dynamic Latched Comparator",IEEE, 2011.
  10. B. T. Turko and W. F. Kolbe ,"Ultra- Fast Voltage Comparators For Transient Waveform Analysis", Vol. 37, No. 2, IEEE Transaction On Nuclear Science, April 1990.
  11. P. R. Gray and R. G. Meyer, "Analysis and Design of analog Integrated Circuits". John Wiley & Sons,Inc. ,third edition ed. , 1993.
  12. R. J. Baker, E. Institute of, E. Electronics, and I. S. -S. C. Society, CMOS: circuit design, layout, and simulation: IEEE Press, 2008.
  13. A. P. Godse and D. A. Godse, Digital system Design-I:Technical publications 2008.
  14. N. H. E. Weste and D. F. Harris, CMOS VLSI design: a circuits and system perspective: Pearson/Addison-Wesley, 2005.
Index Terms

Computer Science
Information Sciences

Keywords

Power analysis CMOS latch comparators

Powered by PhDFocusTM