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Evolutionary Algorithms for Low Power Test Pattern Generator

International Journal of Computer Applications
© 2013 by IJCA Journal
Volume 66 - Number 7
Year of Publication: 2013
Bagavathi Chandrasekara

Bagavathi Chandrasekara. Article: Evolutionary Algorithms for Low Power Test Pattern Generator. International Journal of Computer Applications 66(7):12-16, March 2013. Full text available. BibTeX

	author = {Bagavathi Chandrasekara},
	title = {Article: Evolutionary Algorithms for Low Power Test Pattern Generator},
	journal = {International Journal of Computer Applications},
	year = {2013},
	volume = {66},
	number = {7},
	pages = {12-16},
	month = {March},
	note = {Full text available}


VLSI testing has been an essential part of chip design recently. A circuit must be tested before fabricating to avoid any malfunctioning. Testing a circuit has become mandatory that the circuit must be designed by ensuring testability. In VLSI testing, the circuit for testing is embedded with the actual design itself to reduce area and it is known to be Built-In Self Test (BIST). The test patterns generated by BIST are applied to the circuit. The test patterns are to be optimized to cover all the faults, reduce testing time and consume less power. This is achieved by employing Evolutionary Algorithms in selecting the patterns such that the inputs of design switch minimally. Test pattern generator is designed using these evolutionary algorithms so that the test vectors selected can be used for reducing the switching activity in the circuit and also by maintain the fault coverage. Genetic Algorithm and Particle Swarm Optimization are concentrated and their efficiencies are explained in this work


  • Y Zorian, "A Distributed BIST Control Scheme for Complex VLSI Devices," Proceedings ofVLSI Test Symposium (VTS'93), pp. 4 – 9, 1993.
  • F Corno, M Rebaudengo, M Reorda, G Squillero and M Violante, "Low Power BIST via Non-Linear Hybrid Cellular Automata," Proceedings of VLSI Test Symposium (VTS'00), pp. 29 – 34, 2000.
  • G Marsaglia and L Tsay, "Matrices and the Structure of Random number Sequences", Proceedings of Linear algebra and its applications, pp 147 – 156, 1985.
  • H Rahaman, Farhana Rashid, Vishwani D Agrawal, "Power Problems in VLSI Circuit Testing", VDAT 2012, LNCS 7373, pp 393 – 405, 2012.
  • P Girard et. al, "Low Energy BIST Design: Impact of the LFSR TPG Parameters on the Weighted Switching Activity," Proceedings of International Symposium on Circuits and Systems, 1999.
  • Enmin Tan, Li Wang A, "Built-in Self-test Design with Low Power Consumption Based on Genetic Algorithm", Proceedings of Ninth International Conference on Electronic Measurement & Instruments, pp 526 – 529, 2009.
  • Miron Abramovici, Melvin A Breuer, Arthur D Friedman, "Digital systems testing and testable design", IEEE Press, Revised edition, New York.
  • R H He, X W Li and Y Z Gong, "A low power BIST TPG design", Proceedings of the 5th international conference on ASIC, Vol. 2, pp 1136-1139, 2003
  • E M Tan, S D Song and W K Shi, "Power Reduction in BIST Design Based on Genetic Algorithm and Vector-Inserted TPG", Proceedings of 2007 8th International Conference on Electronic Measurement & Instruments, Vol. 4, pp 533 – 537, 2007.
  • M H Marghny, Rasha M Abd El-Aziz and Ahmed I Taloba, "An Effective Evolutionary Clustering Algorithm: Hepatitis C: Case Study", International Journal of Computer Applications, Vol. 34, No. 6, November 2011.
  • Vishwani D Agrawal and M Bushnell, "Essentials of Electronic Testing for Digital, Memory and Mixed-signal VLSI circuits", Kluwer Academic Publishers, 2000.
  • X D Zhang, W L Shan, and K Roy, "Low-power weighted random pattern testing", IEEE Transactions on CAD of ICs and Systems, Vol. 19, pp 1389-1398, 2000.
  • N Ahmed, M H Tehranipour and M Nourani, "Low power pattern generation for BIST architecture", Proceedings of the 2004 International Symposium on Circuits and Systems, (ISCAS '04), Vol. 2, pp 23 - 26, 2004.
  • P Girard, "Survey of Low-Power testing of VLSI Circuit", IEEE Design & Test of Computers, Vol. 19, pp 82 – 92, 2002.
  • Gary Yeap, "Practical low power digital VLSI design", Springer, 2009.
  • S Gerstendiirfer and H J Wunderlich, "Minimized Power Consumption for Scan-based BIST", Proceedings of IEEE International Test Conference, September 1999.
  • Pinaki Mazumder, and Elizabeth M Rudnick, "Genetic Algorithms for VLSI Design, Layout & Test automation", Prentice Hall, 1999.
  • Melanie Mitchell, "An Introduction to Genetic Algorithms", MIT press, Cambridge, England.
  • Franz Rothlauf, "Representations for Genetic and Evolutionary Algorithms", Springer, 2006.
  • M J O'Dare and T Arslan, "Generating Test Patterns for VLSI circuits using a Genetic Algorithm", Electronics Letters, Vol. 30, No. 10, pp 778 – 779, 1994.
  • Randy L Haupt, Sue Ellen Haupt, "Practical Genetic Algorithms", Wiley Interscience publication, Second edition.
  • Dhiraj Sangwan, Seema Verma and Rajesh Kumar, "A Genetic Algorithm based Two Phase Fault Simulator for Sequential Circuit" International Journal of Computer Applications, Vol. 12, No. 10, November 2011.
  • J Kennedy and R Eberhart "Particle Swarm Optimization", Proceedings of the 1995 IEEE International Conference on Neural Networks, pp. 1942-1948, 1995.
  • Balwnder Singh, Sukhleen Bindra Narang and Arun Khosla, "Particle Swarm Optimization Framework for LowPower Testing of VLSI Circuits", International Journal of Artificial Intelligence & Applications (IJAIA), Vol. 2, No. 3, July 2011.
  • Adnan Fakeih and Ahmed Kattan, "Recurrent Genetic Algorithms: Sustaining Evolvability", EvoCOP 2012, LNCS 7245, pp. 230–242, 2012.
  • Claudio Lopes De Souza, "Comparisons of intra-, inter population and modified recurrent selection methods Electronics Industry," Review of Brazilian Genetics, Vol. 16, No. 1, pp. 369-395, 1993.