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Evolutionary Algorithms for Low Power Test Pattern Generator

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International Journal of Computer Applications
© 2013 by IJCA Journal
Volume 66 - Number 7
Year of Publication: 2013
Authors:
Bagavathi Chandrasekara
10.5120/11095-6053

Bagavathi Chandrasekara. Article: Evolutionary Algorithms for Low Power Test Pattern Generator. International Journal of Computer Applications 66(7):12-16, March 2013. Full text available. BibTeX

@article{key:article,
	author = {Bagavathi Chandrasekara},
	title = {Article: Evolutionary Algorithms for Low Power Test Pattern Generator},
	journal = {International Journal of Computer Applications},
	year = {2013},
	volume = {66},
	number = {7},
	pages = {12-16},
	month = {March},
	note = {Full text available}
}

Abstract

VLSI testing has been an essential part of chip design recently. A circuit must be tested before fabricating to avoid any malfunctioning. Testing a circuit has become mandatory that the circuit must be designed by ensuring testability. In VLSI testing, the circuit for testing is embedded with the actual design itself to reduce area and it is known to be Built-In Self Test (BIST). The test patterns generated by BIST are applied to the circuit. The test patterns are to be optimized to cover all the faults, reduce testing time and consume less power. This is achieved by employing Evolutionary Algorithms in selecting the patterns such that the inputs of design switch minimally. Test pattern generator is designed using these evolutionary algorithms so that the test vectors selected can be used for reducing the switching activity in the circuit and also by maintain the fault coverage. Genetic Algorithm and Particle Swarm Optimization are concentrated and their efficiencies are explained in this work

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