The week's pick
Random Articles
Reseach Article
Article:A Novel Area efficient Folded Modified convolutional interleaving architecture for MAP decoder
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 9 - Number 9 |
| Year of Publication: 2010 |
| Authors: S.Shiyamala, Dr.V.Rajamani |
10.5120/1414-1910
|
S.Shiyamala, Dr.V.Rajamani . Article:A Novel Area efficient Folded Modified convolutional interleaving architecture for MAP decoder. International Journal of Computer Applications. 9, 9 ( November 2010), 18-22. DOI=10.5120/1414-1910
Abstract
This paper proposes a novel area-efficient folded modified convolutional interleaving (FMCI) architecture for MAP decoder. The end to end delay of proposed FMCI requires only 2M. In addition, the number of latches can reduce to M-2. Hence the proposed FMCI architecture has lesser end to end delay and minimizes the number of latches usage as compare with block interleaving and convolutional interleaving. In addition to this the life time analysis and forward-backward allocation has also been implemented. Therefore, FMCI architecture can reduce the memory elements about 88% as compare with block interleaving for the particular condition when M = NJ
References
- Bernard Sklar, (2003). Design Communication Fundamentals and applications, Person Education, 2003, 437 – 461
- Seok-Jun Lee,Naresh R.SAhanbhag,Andrew C . Singer, (2005) .Area-Efficient High – Throughput MAP Decoder Architectures, IEEE trans on VLSI, Vol.13 No.8, 921 – 933, Aug2005
- Kazuhiko yamaguchi,Shinya Maehara, (2006).study on turbo decoding using hard decision decoder - principle of hard-in – soft-out decoding,International Symposium on Information Theory and its Application,ISITA 2006,114-118.
- Sina Vafi,Tadeusz Wysocki, (2004). Modified convolutional Interleavers and their performance in turbo codes,computer and Electronics engineering faculty publications,symposium on trends in communications,2004, 54-57.
- Michacl Tuchler,Ralf Koetter,and Andrew C.Singer , (2002). Turbo Equalization : Principles and New Results,IEEE tran on communications,vol 50, No : 5,May 2002, 754-767
- Atluri,I., Arslan.T, “Low power VLSI Implementation of MAP decoder for turbo codes through forward recursive calculation of Reverse state metrics “IEEE
- Mustafa Taskaldiran,Richard C.S.Morling and lzzet kale, “ The modified Max-Log_MAP turbo decoding Algorithm by Extrinsic Information scaling for wireless applications”
- Zhongfeng wang,Zhipei Chi and Keshab K.parthi, (2002). Area – Efficient High-speed decoding schemes for turbo decoders”,IEEE Tran on VLSI,vol 10,no:6,Dec 2002, 902-912
- Guido Masera,Marco Mazza,Gianluca Piccinni, (2002) .Architecture strategies for low-power VLSI turbo decoders IEEE Tran on VLSI ,vol 10,no:3,June 2002, 279-285.
- Keshab K, Parthi, “VLSI Digital Signal processing systems design and implementation”, 149 – 164.
- C.Berrou.A.Glavieux,and P.Thitimajshima, (1993).Near Shannon limit error – correcting coding and decoding : Turbo codes ,” in proc.IEEE nt.Conf.Communication,Geneva, Switzerland, May 1993, 1064 – 1070.
- Sina vafi and Tadeusz Wysocki, (2004).Modified Convolutional interleavers and their performance in Turbo Codes , Joint IST workshop on the Mobile Future and symposium on trends in communications,2004.SympoTic ’04 ; 54 –57.
Index Terms
Keywords