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Application of Current-Mode Multi-Valued Logic in the Design of Vedic Multiplier

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IJCA Special Issue on Recent Trends in Engineering Technology
© 2013 by IJCA Journal
RETRET
Year of Publication: 2013
Authors:
Ashish S. Shende
M. A. Gaikwad
D. R. Dandekar

Ashish S Shende, M A Gaikwad and D R Dandekar. Article: Application of Current-Mode Multi-Valued Logic in the Design of Vedic Multiplier. IJCA Special Issue on Recent Trends in Engineering Technology RETRET:13-16, March 2013. Full text available. BibTeX

@article{key:article,
	author = {Ashish S. Shende and M. A. Gaikwad and D. R. Dandekar},
	title = {Article: Application of Current-Mode Multi-Valued Logic in the Design of Vedic Multiplier},
	journal = {IJCA Special Issue on Recent Trends in Engineering Technology},
	year = {2013},
	volume = {RETRET},
	pages = {13-16},
	month = {March},
	note = {Full text available}
}

Abstract

Vedic multiplier is based on ancient Indian Vedic mathematics that offers simpler and hierarchical structure. Multi-valued logic results in the effective utilization of interconnections, which reduces the chip size and delay. This paper proposes that if the potential of multi-valued logic is combined with simplicity of Vedic architecture, it may result in an efficient multiplier design. Since the performance of a digital signal processor depends mainly on the multipliers used, the proposed approach can greatly enhance the performance of a digital signal processor.

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