Call for Paper - November 2017 Edition
IJCA solicits original research papers for the November 2017 Edition. Last date of manuscript submission is October 20, 2017. Read More

A Comparative Study of Different Topologies for Network-On-Chip Architecture

Print
PDF
IJCA Special Issue on Recent Trends in Engineering Technology
© 2013 by IJCA Journal
RETRET
Year of Publication: 2013
Authors:
Sonal S. Bhople
M. A. Gaikwad

Sonal S Bhople and M A Gaikwad. Article: A Comparative Study of Different Topologies for Network-On-Chip Architecture. IJCA Special Issue on Recent Trends in Engineering Technology RETRET:27-29, March 2013. Full text available. BibTeX

@article{key:article,
	author = {Sonal S. Bhople and M. A. Gaikwad},
	title = {Article: A Comparative Study of Different Topologies for Network-On-Chip Architecture},
	journal = {IJCA Special Issue on Recent Trends in Engineering Technology},
	year = {2013},
	volume = {RETRET},
	pages = {27-29},
	month = {March},
	note = {Full text available}
}

Abstract

Network on Chip (NoC) is one solution for designing communication among components in the SoC circuits with several billion transistors that will reach the market in approximately 5-10 years from now. Different topologies having various advantages according to their applications. This paper present brief idea about topologies depending on parameter.

References

  • A Delay-Aware Topology-based Design for Network-on-chip Applications By Haytham Elmiligi, Ahmed A. Morgan, M. Watheq El-Kharashi, Fayez Gebali. IEEE transaction, 2009.
  • M. Mirza-Aghatabar+,S. Koohi+, S. Hessabi*, M. Pedram†," An Empirical Investigation of Mesh and Torus NoC Topologies Under Different Routing Algorithms and Traffic Models", IEEE International Conference on Digital System DSD 2007.
  • L. Benini and D. Micheli, Networks on Chips: A New SoC Paradigm, IEEE Computer, 35 p. 70 (2002).
  • B. H. Meyer, J. J. Pieper, J. M. Paul, J. E. Nelson, S. M. Pieper and A. G. Rowe, "Power-performance simulation and design strategies for single-chip heterogeneous multiprocessors," IEEE transactions on Computers, vol. 54, no. 6, pp. 684-697, Jun 2005.
  • M. Palesi, R. Holsmark, S. Kumar, and V. Catania, " Application specific routing algorithms for network on chip," IEEE Transactions on Parallel and Distributed Systems, vol. 20, no3 pp. 316-339,2009.
  • Khalid Latif, Tiberiu Seceleanu, Hannu Tenhunen, Power and Area Efficient Design of Network-on-Chip Router Through Utilization of Idle Buffers.
  • M. Nickray, M. Dehyadgari, and A. Afzali-kusha, "Power and Delay optimization for network on chip," in Proceedings of the 2005 European Conference on Circuit Theory and Designs, Cork, Ireland, Aug-28-2 Sept. 2005, pp. 273-276.
  • T. Bjerregaard and K. Mahadevan, " A survey of research and practices of network-on-chip,"ACM Computing Surveys, vol. 38, pp. 38, pp. 1-51, Mar. 2006.
  • A. Chien, " A cost and speed model for k-ary n-Cube Wormhole Routers," IEEE transactions on Parallel and Distributed Systems, vol. 9, no2, pp 29-36, Feb 1998.
  • Cheng Liu•, Liyi Xiao, Fangfa Fu, Design and Analysis of On-Chip Router.
  • L. S. Peh and W. J. Dalley, A delay model for router michroarchitectures," IEEE Micro, vol. 21, no. 1, pp. 26-34, Jan. 2001.
  • W. Zhou, Y. Zhang, and Z. Mao," An application specific NOC mapping for optimized delay," in proceeding of the IEEE International Conference on Design and Test of Integrated Systems in Nanoscale Technology ,Tunis, Tunisia , Sept. 5-7, 2006, pp. 184-188.
  • V. Pavlidis and E. Friedman," Interconnect-based design methodologies for three-dimensional integrated circuits'' Proceeding of the IEEE, vol. 97, no. 1, pp 123-140, 2009.
  • V. Dumitriu and G. N. Khan, "Throughput- oriented NOC topology generation and analysis for high performance SOC ," IEEE Transactions on VLSI Systems, vol. in press 2009.
  • H. Elmiligi, A. A. Morgan, M. W. EI-Kharashi and F. Gebli, " A reliability-aware design methodology for network-on-chip applications," in proceeding of the IEEE International Conference on Design and Test of Integrated Systems in Nanoscale Technology ,Era Cario, Egypt, Apr. 6-9, 2009, pp. 107-112.
  • H. Elmiligi, A. Morgan, M. W. EI-Kharashi and F. Gebli, " Power Aware Topology Optimization for Network-on-chips," in proceeding of the IEEE International Symposium on Circuits and SystemsConference on Design and Test of Integrated Systems in Nanoscale Technology ,Era Cario, Egypt, Apr. 6-9, 2009, pp. 107-112.
  • Victor Dumitriu and Gul N. Khan, "Throughput-Oriented NoC Topology Generation and Analysis for High Performance SoCs", IEEE transactions on very large scale integration (vlsi) systems, vol. 17, no. 10, october 2009.
  • Mahmoud Moadeli1, Ali Shahrabi2, Wim Vanderbauwhede1, Mohamed Ould-Khaoua1," An Analytical Performance Model for the Spidergon NoC",IEEE 21st International Conference on Advanced Networking and Applications(AINA'07) 2007.