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Review of Mesh Topology of NoC Architecture using Source Routing Algorithms

IJCA Special Issue on Recent Trends in Engineering Technology
© 2013 by IJCA Journal
Year of Publication: 2013
Vaishali V. Ingle
Mahendra A. Gaikwad

Vaishali V Ingle and Mahendra A.gaikwad. Article: Review of Mesh Topology of NoC Architecture using Source Routing Algorithms. IJCA Special Issue on Recent Trends in Engineering Technology RETRET:30-34, March 2013. Full text available. BibTeX

	author = {Vaishali V. Ingle and Mahendra A.gaikwad},
	title = {Article: Review of Mesh Topology of NoC Architecture using Source Routing Algorithms},
	journal = {IJCA Special Issue on Recent Trends in Engineering Technology},
	year = {2013},
	volume = {RETRET},
	pages = {30-34},
	month = {March},
	note = {Full text available}


NoC is efficient on-chip communication architecture for SoC architectures. It enables integration of a large number of computational and storage blocks on a single chip. NoCs have tackled the SoCs many disadvantages and are structured, reusable, scalable, and have high performance. Lots of topologies have been proposed for NoCs. Among these topologies, mesh topology has gained more consideration by designers due to its simplicity. A 2D-mesh topology is one of the most frequently mentioned topologies for an NoC design due to its natural layout mapping onto an SoC. Thus, the 2D mesh network on chip (NoC) is a popular NoC topology because of network scalability and the use of a simple routing algorithm. In this paper, we compare popular mesh with the other NoC topologies in terms of different performance metrics such as, latency, power consumption, and power/throughput ratio under different routing algorithms.


  • Mikael Milberg et. al. ,"Priority Based Forced Requeue to Reduce Worst-Case Latencies for Bursty Traffic" Proceedings of the Conference on Design, Automation and Test in Europe 2009 Pages 1070-1075
  • Wang Zhang et. al. ,"Comparison Research between XY and Odd-Even Routing Algorithm of a 2-Dimension 3x3 mesh Topology Network –on –Chip" 2009 IEEE computer society
  • Naveen Choudhary,"Bursty Communication Performance Analysis of Network-on-Chip with Diverse Traffic Permutations" International Journal of Soft Computing and Engineering (IJSCE) ISSN: 2231-2307, Volume-1, Issue-6, January 2012
  • Jan Ho Bahn et. al. ,"On Design and Analysis of a Feasible Network-on -Chip(NoC) Architecture"2007 International Conference on Digital Object Identifier
  • Chuggani R et. al. "Traffic Model for Concurrent Core Task in Network on Chip" IEEE 2011. pages:205-210
  • NIRGAM Manual: A Simulator for NoC Interconnect Routing and application Modeling Version 1. 1
  • Saad Mubeen, "Evaluation of source routing for mesh topology network on chip platforms", Master of Science Thesis, 2009.
  • Dally W. J et. al. "Route packets, not wires: on-chip interconnection networks", in Design Automation Conference, Las Vegas, Nevada, USA, 2001, pp. 684-689.
  • Dally W. J. and Towles B. , "Principles and Practices of Interconnection Networks", Morgan Kaufmann Publishers an Imprint of Elsevier Inc, 2004.
  • [Lalit Kishore Arora, et. al. "Simulation and Analysis of Packet loss in Mesh Interconnection Networks", IJARCSSE Proceedings on (DRISTI 2012), DRISTI (1):35 - 38, April 2012. ISB
  • Axel Jantsch et. al. "Networks on Chip", Kluwer Academic Publishers. 2003.
  • Kavaldjiev N et. al. "Routing of guaranteed throughput traffic in a network-on-chip". Available at: http://doc. utwente. nl/54538/.
  • Mubeen,S. ,et. al," Designing Efficient Source Routing for Mesh Topology Network on Chip Platforms" IEEE 2010Page(s): 181 - 188
  • Paliwal, K. K. ; et. al. "Performance Analysis of Guaranteed Throughput and Best Effort Traffic in Network-on-Chip under Different Traffic Scenario. "IEEE 2009, Page(s): 74 - 78
  • Wang Zhang "The Buffer Depth Analysis of 2-Dimension Mesh Topology Network-on-Chip with Odd-Even Routing Algorithm. " IEEE 2009 Page(s): 1 - 4
  • A. Hemani, et. al, "Network on a chip: an architecture for billion transistor era,"Proc. IEEE NorChip, 2000.
  • Lalit Kishore Arora, et. al. " Performance Evaluation of mesh with source routing for Packet Loss. " IJ ARCSSET Volume-1, Issue-5, August 2012
  • Benini L. , Micheli G. D. , "Networks on chips: a new SoC paradigm". IEEE Computer Society, 2002.
  • Pan Hao, et. al. "Comparison of 2D MESH Routing Algorithm in NoC. " IEEE 2011
  • Parag Parandkar, et. al. " Performance Comparison of XY, OE and DY Ad Routing Algorithm by Load Variation Analysis of 2-Dimensional Mesh Topology Based Network-on-Chip. "BVICAM's International Journal of Information Technology,@Jan2012
  • Saad Mubeen, et. al. "On Source Routing for Mesh Topology Network on Chip. " 9th Swedish SoC Conference, Swedish Chapter of IEEE SSCS
  • Mirza-Aghatabar, et. al. "An Empirical Investigation of Mesh and Torus NoC Topologies Under Different Routing Algorithms and Traffic Models . " IEEE 2007,Pages: 19-26.