Fault Detection Multipliers in Polynomial and Normal Basis

International Journal of Computer Applications
© 2010 by IJCA Journal
Number 5 - Article 18
Year of Publication: 2010
Siddharth Shelly
Babu T Chacko

Siddharth Shelly and Babu T Chacko. Article: FAULT DETECTION MULTIPLIERS IN POLYNOMIAL AND NORMAL BASIS. International Journal of Computer Applications 1(5):102–106, February 2010. Published By Foundation of Computer Science. BibTeX

	author = {Siddharth Shelly and Babu T Chacko},
	journal = {International Journal of Computer Applications},
	year = {2010},
	volume = {1},
	number = {5},
	pages = {102--106},
	month = {February},
	note = {Published By Foundation of Computer Science}


With significant advances in wired and wireless technologies and also increased shrinking in the size of VLSI circuits, many devices have become very large because they need to contain several large units. This large number of gates and in turn large number of transistors causes the devices to be more prone to faults. These faults especially in sensitive and critical applications may cause serious failures and hence should be avoided. In many cryptographic schemes, the most time consuming basic arithmetic operation is the finite field multiplication and its hardware implementation for bit parallel operation may require millions of logic gates. Some of these gates may become faulty in the field due to natural causes or malicious attacks, which may lead to the generation of erroneous outputs by the multiplier. New architectures are developed to detect erroneous outputs caused by certain types of faults in bit-serial polynomial basis multipliers and digit-serial normal basis multipliers over finite fields of characteristic two. In particular, parity prediction schemes are developed for detecting errors due to single and certain multiple stuck-at faults.


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