CFP last date
22 April 2024
Call for Paper
May Edition
IJCA solicits high quality original research papers for the upcoming May edition of the journal. The last date of research paper submission is 22 April 2024

Submit your paper
Know more
The week's pick
Responsive image
Enhancing Privacy Preservation: Multi-Attribute Protection with P-Sensitive K-Anonymity

Twinkle Patel Kiran Amin
Random Articles
Reseach Article

Design of Low Power Sense Amplifier based NAND Latch under 30nm Technology

by K. Gavaskar, P. Kaviya Priya, M. Sukhanya
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 144 - Number 2
Year of Publication: 2016
Authors: K. Gavaskar, P. Kaviya Priya, M. Sukhanya
10.5120/ijca2016910106

K. Gavaskar, P. Kaviya Priya, M. Sukhanya . Design of Low Power Sense Amplifier based NAND Latch under 30nm Technology. International Journal of Computer Applications. 144, 2 ( Jun 2016), 1-4. DOI=10.5120/ijca2016910106

@article{ 10.5120/ijca2016910106,
author = { K. Gavaskar, P. Kaviya Priya, M. Sukhanya },
title = { Design of Low Power Sense Amplifier based NAND Latch under 30nm Technology },
journal = { International Journal of Computer Applications },
issue_date = { Jun 2016 },
volume = { 144 },
number = { 2 },
month = { Jun },
year = { 2016 },
issn = { 0975-8887 },
pages = { 1-4 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume144/number2/25148-2016910106/ },
doi = { 10.5120/ijca2016910106 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:46:31.233700+05:30
%A K. Gavaskar
%A P. Kaviya Priya
%A M. Sukhanya
%T Design of Low Power Sense Amplifier based NAND Latch under 30nm Technology
%J International Journal of Computer Applications
%@ 0975-8887
%V 144
%N 2
%P 1-4
%D 2016
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In electronics, a latch is a circuit that has two stable states and can be used to store information. Therefore latches can be memory devices and can store one bit of data as long as the device is powered. This paper mainly concentrated on the design of low power sense amplifier based NAND latch where sense amplifier is part of the read circuit that is used when data is read from the memory and amplify the voltage swing. An analytical model of different sense amplifier based NAND latch was designed and simulated using 30nm CMOS technology with various supply voltage. The NAND latch designed using low power Conventional Voltage Sense Amplifier is proposed in this paper. The simulation is carried out in SYNOPSYS EDA software under 30nm technology with different supply voltages.

References
  1. Borivoje Nikolic,Vojin G. Oklobdzija,Vladimir Stojanović, WenyanJia,IEEE journal of solid-state circuits,June 2012
  2. Jyotihooda, Saritaola, ManishasainI, ”Design and Analysis of a Low Power Sense Amplifier for Memory Application”,International Journal of Innovative Technology and Exploring Engineering (IJITEE), April 2013
  3. B.S.Reniwal and S.K.Vishvakarma.” A Reliable, Process-Sensitive-Tolerant Hybrid Sense Amplifier for Ultralow Power SRAM “,International Journal of Electronics and Electrical Engineering,March2013.
  4. BiriBalaji,S.Saleem Malik,” Design of Dual Dynamic Flip-Flop with Featuring Efficient Embedded Logic for Low Power CMOS Vlsi Circuits”, September 2014.
  5. Rakesh Dayaramji Chandankhedde ,Debiprasa Priyabrata Acharya,”Design of High Speed Sense Amplifier for SRAM”, International Journal of Innovative Technology and Exploring Engineering (IJITEE),March 2013.
  6. V. Bhagyalakshmi,M. Ravi Teja, CH. Madhan Mohan,” Design and VLSI Simulation of SRAM Memory Cells for Multi-ported SRAM’s”, International Journal of Research in ElectronicsandCommunication Technology,March2015.
  7. Nahid Rahman,B.P.Singh,”Design of Low Power Sram Memory Using 8t SramCell”,International Journal of Recent Technology and Engineering,March 2013.
  8. PowerFlipFlopUsingMTCMOS Technique”,International Journal of Computer Applications & Information Technology,July 2012.
  9. Shi-Hao Chen, Youn-Long LinandMango C.-T.Chaz,” Power-Up Sequence Control for MTCMOS Designs”,IEEE transactions on very largescaleintegration (vlsi) systems, vol. 21, no. 3, march 2013.
  10. Jin-FaLin,”Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme”, IEEE transactions on very large scale integration systems,July 2013.
  11. A.Hemaprabha,K.Vivek, M. Vaijayanthi, S. Sabeetha,” Implementation of latch type sense amplifier”, International Journal of Research in Engineering and Technology,Jan2014.
  12. Litty Varghese, V. Mathiazhagan, Neethu John,” Application of Low Power Pulse Triggered Flipflop Based On Signal Feedthrough Scheme in Enhanced Scan Design”,January 2016.
  13. Mayur D. Ghatole,Dr. M. A. Gaikwad,”Design a Low Power Flip Flop Based on a Signal Feed Through Scheme”, International Research Journal of Engineering and Technology, January 2016.
  14. Gavaskar, K. and S. Priya, Design of Efficient Low Power Stable 4-Bit Memory Cell. International Journal of Computer Applications, 2013. 84(1).
  15. Gavaskar, K. and U.S. Ragupathy. An efficient design and comparative analysis of low power memory cell structures. in Green Computing Communication and Electrical Engineering (ICGCCEE), 2014 International Conference on. 2014. IEEE.
  16. Gavaskar, K., et al. Design and Comparative Analysis of Low Power Dynamic Random Access Memory Array Strucyure. in International Journal of Engineering Research and Technology. 2015. ESRSA Publications.
  17. Gavaskar, K. and S. Priya. Design Of Efficient Low Power 9t SRAM Cell. in International Journal of Engineering Research and Technology. 2013. ESRSA Publications.
Index Terms

Computer Science
Information Sciences

Keywords

Memory Sense Amplifier NAND latch Low Power.

Powered by PhDFocusTM