Design and Synthesis of High Performance Vedic DSP Processor

Print
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Year of Publication: 2017
Authors:
Anuradha Savadi, Raju Yanamshetti, Jyoti Godihal
10.5120/ijca2017914469

Anuradha Savadi, Raju Yanamshetti and Jyoti Godihal. Design and Synthesis of High Performance Vedic DSP Processor. International Journal of Computer Applications 168(6):27-32, June 2017. BibTeX

@article{10.5120/ijca2017914469,
	author = {Anuradha Savadi and Raju Yanamshetti and Jyoti Godihal},
	title = {Design and Synthesis of High Performance Vedic DSP Processor},
	journal = {International Journal of Computer Applications},
	issue_date = {June 2017},
	volume = {168},
	number = {6},
	month = {Jun},
	year = {2017},
	issn = {0975-8887},
	pages = {27-32},
	numpages = {6},
	url = {http://www.ijcaonline.org/archives/volume168/number6/27880-2017914469},
	doi = {10.5120/ijca2017914469},
	publisher = {Foundation of Computer Science (FCS), NY, USA},
	address = {New York, USA}
}

Abstract

To satisfy the prerequisite of rapid speed signal processing design of high performance DSP processor is renowned. This paper represents a novel design and FPGA based pursuit of 64 bit DSP processor. The proposed design implicates multistage pipeline architecture and vedic algorithms to improve the speed. The DSP processor is rich with multiple application specific instructions (ASIP). The verilog HDL is used and the validated through extensive simulation. Synthesis results and attainment scrutiny of each systems components confirmed significant performance meliorism in the proffered DSP processor over the extant one..

References

  1. Eamon O’ Malley and Kari Rinne, “A 16-bit Fixed point digital signal processor for digital power convertercontrol”IEEEconference,DOI: 10.1109/APEC.2005.1452885, vol. 1, pp. 50–56, March 2005.
  2. Johann Grobschadl and Guy-Armand Kamendje. “A Single -cycle (32*32+32+64) bit multiply/accumulate unit for digital signal processing and public-key cryptography” Electronics circuits and Systems ICECS 2003, IEEE conference, vol. 2,pp.739-742, Dec 2003.
  3. Hong Yue,Mingche Lai, Kui Dai, and Zhi-ying Wang, “Design of a configurable embedded processor architecture for DSP functions” parallel and distributed systems, 2005, IEEE conference, vol. 2, pp.27-31, July 2005.
  4. Donghoon Lee, Chanwon Ryu, Jusung Park, Kyunsoo Kwon and Wontae Choi, “Design and implementation of 16-bit fixed point digital signal processor” International SOC Design 2008, IEEE conference, vol. 2, pp.II-61-II64, November 2008.
  5. Tasnim Ferdous, “Design and FPGA-based Implementation of a High performance 32-bit DSP processor” computer and information technology,ICCIT, IEEE conference, pp.484-489, Dec 2012.
  6. Sandesh S Saokar, R.M.Banakar, and Saroja Siddamal, “High speed signed multiplier for digital signal processing applications” signal processing , computing and control(ISPCC) 2012, IEEE conference, pp.1-6, March 2012.
  7. Honey Durga Tiwari, Ganzorig Gankhuyag, Chan Mo Kim,and Yong Beom Cho “Multiplier design based on ancient Indian vedic Mathematics” International SOC Design 2008, IEEE conference, vol. 2, pp.II-65-II68, November 2008.
  8. Prabir saha, Arindam Banerjee, Partha Bhattacharyya and Anup Dandapat, “High speed ASIC design of complex multiplier using Vedic Mathematics”, Students technology Symposium(TechSym), IEEE conference, pp.237-241, Jan 2011.
  9. Akhalesh K.Itwadiya, Rajesh mahale ,Vivek Patel , Dadan Kumar “Design a DSP operations Using Vedic Mathematics”,International Conference on Communication and signal processing IEEE 2013 , pp 897-902 , April 2013
  10. Abhyarthana Bisoyi, Mitu Baral and Manoja Kumar Senapati, “Comparision of a 32-bit vedic multiplier with a conventional binary multiplier”, Advanced communication control and computing technologies (ICACCCT), IEEE conference, pp.1757-1760, May 2014.
  11. Surabhi Jain, Mukul Pancholi, Harsh Garg and Sandeep Saini, “ Binary division algorithm and high speed Deconvolution algorithm”, Electrical Engineering/Electronics, computer, telecommunications andinformation technology(ECTICON), IEEE conference pp. 1-5, May 2014.
  12. Shruti Murgai, Ashutosh Gupta, Gayathri Muthukrishnan, “Energy Efficient And High Performance 64-bit Arithmetic Logic Unit Using 28nm Technology”, Advances in computing, communication and informatics(ICACCI), IEEE conference, pp. 453-456, Agust 2015.
  13. Vaijyanath Kunchigi, Linganagoda Kulkarni, Subhas Kulkarni “32-BIT MAC Unit Design Using Vedic Multiplier”, International journal of Scientific and Research Publicatoions ,Vol 3, Issue 2,pp. 1-7, February
  14. Siba kumar panda, arati sahu, “A novel vedic divider architecturewith reduced delay for VLSI apllications”, international journal of computer applications, vol.120 no.17, june 2015.
  15. Tushar Shukla, Prabhat Kumar Shukla, Harish Prabhakar, “High Speed Multiplier for FIR Filter Design using Window”, International Conference on Signal Processing and Integrated Networks (SPIN) IEEE 2014.
  16. Padma Kunthe, Sameena Zafar, Ankita Sharma, “16- order IIR filter Design using Vedic Mathematics Technique”, International Journal of Engineering Innovation and Research. Volume 3, Issue 2 ISSN: 2277-5668. PP.No.138. 2014.
  17. Padma Kunthe, Sameena Zafar, Ankita Sharma, “32-order IIR filter Design using Vedic mathematics”, International Journal of Artificial Intelligence and Mechatronics. Volume 2, Issue 5, ISSN: 2320-5121. 2014.
  18. Savita Srivastava, Dr. Deepak Nagaria “Design of High Performance FIR filter using Vedic Mathematics in MATLAB”, International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering. Vol.3, Issue 10, October 2014. ISSN (print):2320-3765, ISSN(online): 2278-8875.

Keywords

DSP Processor, Pipelining, Vedic mathematics, ASIP.