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Reseach Article

Clock Power Optimizations in VLSI design at Advanced Technology Nodes

by Manjunath Rao B. M., H. V. Ravish Aradhya
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 169 - Number 9
Year of Publication: 2017
Authors: Manjunath Rao B. M., H. V. Ravish Aradhya
10.5120/ijca2017914880

Manjunath Rao B. M., H. V. Ravish Aradhya . Clock Power Optimizations in VLSI design at Advanced Technology Nodes. International Journal of Computer Applications. 169, 9 ( Jul 2017), 29-34. DOI=10.5120/ijca2017914880

@article{ 10.5120/ijca2017914880,
author = { Manjunath Rao B. M., H. V. Ravish Aradhya },
title = { Clock Power Optimizations in VLSI design at Advanced Technology Nodes },
journal = { International Journal of Computer Applications },
issue_date = { Jul 2017 },
volume = { 169 },
number = { 9 },
month = { Jul },
year = { 2017 },
issn = { 0975-8887 },
pages = { 29-34 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume169/number9/28015-2017914880/ },
doi = { 10.5120/ijca2017914880 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-07T00:16:58.602351+05:30
%A Manjunath Rao B. M.
%A H. V. Ravish Aradhya
%T Clock Power Optimizations in VLSI design at Advanced Technology Nodes
%J International Journal of Computer Applications
%@ 0975-8887
%V 169
%N 9
%P 29-34
%D 2017
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Power reduction in VLSI designs is one of the key design constraints along with others, namely timing, area, quality constraints, noise, etc. Even though there has been a steady growth of devices that are able to be placed in a given area of a chip as per Moore’s law, the same cannot be said for battery technologies as they have never been able to catch up. Since the advent of the deep sub-micron era, speed and higher frequency of operation have become the prime goals of any design as the hunger for faster and better optimized systems are never ending. But as a consequence of faster operating speeds which basically means higher clock frequencies, power becomes one of the main constraints to be considered as the most important component of power dissipation, namely the dynamic power dissipation has a proportional relationship with the clock frequency. Hence clock power optimization is taken up as the prime objective of this paper for technologies below 14 nm as at these technologies, other secondary power dissipation components start to become more prominent. Various design techniques have been discussed and applied at both the circuit design and the RTL levels of abstraction in order to provide a complete review of most of the low power design techniques which can be used to reduce power at both these levels of abstraction. An improvement of 25% and 15.7% of power reduction are observed in clock power and overall power respectively. There is also a power reduction of 2-5% for each of the RTL level optimization techniques.

References
  1. P. Corsonello, S. Perri and G. Cororullo, "Area-time-power tradeoff in cellular arrays VLSI implementations", in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, no. 5, pp. 614-624, Oct. 2000. doi: 10.1109/92.894167
  2. A. Nayak, M. Haldar, P. Banerjee, Chunhong Chen and M. Sarrafzadeh, "Power optimization of delay constrained circuits", Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541), Arlington, VA, 2000, pp. 305-309. doi: 10.1109/ASIC.2000.880754
  3. Mayank Chakraverty, Harisankar PS and Vaibhav Ruparelia,” Low Power Design Practices for Power Optimization at the Logic and Architecture Levels for VLSI System Design”, IEEE conference publications,International conference on energy efficient technologies for sustainability,2016.
  4. T. Enomoto, S. Nagayama and N. Kobayashi, "Low-Power High-Speed 180-nm CMOS Clock Drivers", 2007 Asia and South Pacific Design Automation Conference, Yokohama, 2007, pp. 126-127. doi: 10.1109/ASPDAC.2007.357973
  5. Kai-Shuang Chang, Chia-Chien Weng and Shi-Yu Huang, "Accurate RTL power estimation for a security processor", Conference, Emerging Information Technology 2005, pp. 3 pp.-.doi: 10.1109/EITC.2005.1544353.
  6. J. Srinivas, M. Rao, S. Jairam, H. Udayakumar and J. Rao, "Clock gating effectiveness metrics: Applications to power optimization", 2009 10th International Symposium on Quality Electronic Design, San Jose, CA, 2009, pp. 482-487. doi: 10.1109/ISQED.2009.4810342
  7. T. Na, J. H. Ko and S. Mukhopadhyay, "Clock data compensation aware clock tree synthesis in digital circuits with adaptive clock generation", Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, Lausanne, Switzerland, 2017, pp. 1504-1509
  8. I. Han, J. Kim, J. Yi and Y. Shin, "Register grouping for synthesis of clock gating logic", 2016 International Conference on IC Design and Technology (ICICDT), Ho Chi Minh City, 2016, pp. 1-4. doi: 10.1109/ICICDT.2016.7542070
Index Terms

Computer Science
Information Sciences

Keywords

Activity factor Clock tree Clock gating efficiency Data aware clock gating efficiency low activity non enabled register Regional clock buffer Local clock buffer.