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Design of 12 bit Successive Approximation Analog-to-Digital Converter
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 74 - Number 6 |
| Year of Publication: 2013 |
| Authors: Seema Malik, Sunil Nandal |
10.5120/12886-9627
|
Seema Malik, Sunil Nandal . Design of 12 bit Successive Approximation Analog-to-Digital Converter. International Journal of Computer Applications. 74, 6 ( July 2013), 1-6. DOI=10.5120/12886-9627
Abstract
In this paper, a 12 bit Successive Approximation Analog to Digital Converter has been designed which has high resolution, less power consumption and medium speed. The circuit has been designed and simulated on Cadence tool in 0. 35µm AMS technology with a supply voltage of 3. 3V. Different ADC architectures are present but this SAR ADC has a salient feature of providing high resolution with increased accuracy. In this all the building blocks of SAR ADC have been designed such that they meet the desired specifications. The time domain comparator is used such as to obtain low power consumption. The layout of all the blocks has been done on Cadence Virtuoso and process corner analysis is also done to meet the desired specifications.
References
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