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Reseach Article

A Novel Analysis on Low-Power High-Performance Flip-Flops

by Akila.m, Sathiskumar.m, Sukanya. T
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 90 - Number 16
Year of Publication: 2014
Authors: Akila.m, Sathiskumar.m, Sukanya. T
10.5120/15807-4558

Akila.m, Sathiskumar.m, Sukanya. T . A Novel Analysis on Low-Power High-Performance Flip-Flops. International Journal of Computer Applications. 90, 16 ( March 2014), 32-37. DOI=10.5120/15807-4558

@article{ 10.5120/15807-4558,
author = { Akila.m, Sathiskumar.m, Sukanya. T },
title = { A Novel Analysis on Low-Power High-Performance Flip-Flops },
journal = { International Journal of Computer Applications },
issue_date = { March 2014 },
volume = { 90 },
number = { 16 },
month = { March },
year = { 2014 },
issn = { 0975-8887 },
pages = { 32-37 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume90/number16/15807-4558/ },
doi = { 10.5120/15807-4558 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:11:13.981811+05:30
%A Akila.m
%A Sathiskumar.m
%A Sukanya. T
%T A Novel Analysis on Low-Power High-Performance Flip-Flops
%J International Journal of Computer Applications
%@ 0975-8887
%V 90
%N 16
%P 32-37
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The fast growth of the power density in integrated circuits has made area and power dissipation as the vital design measures. In this paper, several different flip-flop topologies are analyzed and an area, power efficient flip-flop design is proposed. This design overcomes the power dissipation due to the large precharge node capacitance, with reduced number of transistors. The comparative power analysis and performance improvements indicate that the proposed design is suitable for high-performance digital designs where the area and power dissipation is of major concern. The simulation results are verified using tanner v7. 0 tool. The performance comparisons are made using CMOS0. 18µm technology.

References
  1. H. Patrovi, R. Burd, U. Salim, F. Weber, L. DiGregorio, and D. Draper (1996),"Flow-through latch and edge-triggered flip-flop hybrid elements," in Proc. IEEE ISSCC Dig. Tech. Papers, pp. 138–139.
  2. F. Class (1998), "Semi-dynamic and dynamic flip-flops with embedded logic," in Proc. Sump. VLSI Circuits Dig. Tech. Papers, Honolulu, HI, pp. 108–109.
  3. H. Mahmud, V. Tirumalashetty, M. Cooke, and K. Roy (2009), "Ultra low power clocking scheme using energy recovery and clock gating," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 17, no. 1, pp. 33–44.
  4. Saeeid Tahmasbi Oskuii (2003), "Comparative study on low-power high-performance flip-flops," Thesis, Linkoping.
  5. V. Stojanovicand and V. Oklobdzija (1999), "Comparative analysis of master slave latches and flip-flops for high-performance and low-power systems," IEEE J. Solid-State Circuits, vol. 34, no. 4, pp-536-548.
  6. A. Ma and K. Asanovic (2002), "A double-pulsed set-conditional-reset flip-flop," Laboratory for Computer Science, Massachusetts Inst. Technology, Cambridge, Tech. Rep. MIT-LCS-TR-844.
  7. Kalarikkal Absel (2013), "Low -Power Dual Dynamic Node Pulsed Hybrid Flip -Flop Featuring Efficient Embedded Logic'', IEEE Tans. VLSI, Syst. , vol. 21, no. 9, pp. 1693-1704.
  8. Wai Man Chung (2003), "The Usage of Dual Edge Triggered Flip-flops in Low Power, Low Voltage Applications," Thesis, Waterloo, Ontario, Canada.
Index Terms

Computer Science
Information Sciences

Keywords

Precharge node capacitance power dissipation high-performance