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Reseach Article

High Performance Implementation of Universal Gate using Low Power Source Gating Technique

by Harmeet Singh Arora, Rohan Kochar, Geetanjali Sharma
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 96 - Number 10
Year of Publication: 2014
Authors: Harmeet Singh Arora, Rohan Kochar, Geetanjali Sharma
10.5120/16830-6590

Harmeet Singh Arora, Rohan Kochar, Geetanjali Sharma . High Performance Implementation of Universal Gate using Low Power Source Gating Technique. International Journal of Computer Applications. 96, 10 ( June 2014), 26-31. DOI=10.5120/16830-6590

@article{ 10.5120/16830-6590,
author = { Harmeet Singh Arora, Rohan Kochar, Geetanjali Sharma },
title = { High Performance Implementation of Universal Gate using Low Power Source Gating Technique },
journal = { International Journal of Computer Applications },
issue_date = { June 2014 },
volume = { 96 },
number = { 10 },
month = { June },
year = { 2014 },
issn = { 0975-8887 },
pages = { 26-31 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume96/number10/16830-6590/ },
doi = { 10.5120/16830-6590 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:21:23.385850+05:30
%A Harmeet Singh Arora
%A Rohan Kochar
%A Geetanjali Sharma
%T High Performance Implementation of Universal Gate using Low Power Source Gating Technique
%J International Journal of Computer Applications
%@ 0975-8887
%V 96
%N 10
%P 26-31
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Area, Speed and Cost were used to be the main concerns in the VLSI industry and Power consumption was the secondary consideration. But, nowadays, Power is given equal importance as area and speed. The increasing demand for mobile electronic devices which require complex functionality and high speed has increased the requirement for power efficient VLSI circuits. Since, a large number of transistors are being packed onto a single chip, the increase in operating frequency and processing capacity results in increased power dissipation. Power dissipation plays an important role in VLSI circuits since it not only causes overheating which reduces chip life but also makes it difficult to use devices in a portable environment [1]. Also, it results in waste of energy in form of heat which is obviously a major concern nowadays.

References
  1. S. M. Kang, Y. Leblebici "CMOS Digital Integrated Circuits analysis and design" third edition, TMH, 2003.
  2. Bipin Gupta, Sangeeta Nakhate "TRANSISTOR GATING: A Technique for Leakage Power Reduction in CMOS Circuits" ISSN 2250-2459, Volume 2, Issue 4, April 2012.
  3. M. Geetha Priya K. Baskaran D. Krishnaveni "A Novel Leakage Power Reduction Technique for CMOS VLSI Circuits" European Journal of Scientific Research ISSN 1450-216X Vol. 74 No. 1 (2012), pp. 96-105
  4. N. Weste and D. Harris, "CMOS VLSI Design". Reading, MA: Addison Wesley, 2004.
  5. Z. Chen, M. Johnson, L. Wei and K. Roy, "Estimation of standby leakage power in CMOS circuit considering accurate modelling of transistor stacks," in Proc. IEEE ISLPED, pp. 239-244, Aug. 1998.
Index Terms

Computer Science
Information Sciences

Keywords

Transistor Gating Drain Gating Power Gating Low Power Source Gating Power Dissipation Source of Power Dissipation.