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True Single Phase Clocking Flip-Flop Design using Multi Threshold CMOS Technique

by Priyanka Sharma, Rajesh Mehra
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 96 - Number 11
Year of Publication: 2014
Authors: Priyanka Sharma, Rajesh Mehra
10.5120/16842-6698

Priyanka Sharma, Rajesh Mehra . True Single Phase Clocking Flip-Flop Design using Multi Threshold CMOS Technique. International Journal of Computer Applications. 96, 11 ( June 2014), 44-51. DOI=10.5120/16842-6698

@article{ 10.5120/16842-6698,
author = { Priyanka Sharma, Rajesh Mehra },
title = { True Single Phase Clocking Flip-Flop Design using Multi Threshold CMOS Technique },
journal = { International Journal of Computer Applications },
issue_date = { June 2014 },
volume = { 96 },
number = { 11 },
month = { June },
year = { 2014 },
issn = { 0975-8887 },
pages = { 44-51 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume96/number11/16842-6698/ },
doi = { 10.5120/16842-6698 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:21:31.586192+05:30
%A Priyanka Sharma
%A Rajesh Mehra
%T True Single Phase Clocking Flip-Flop Design using Multi Threshold CMOS Technique
%J International Journal of Computer Applications
%@ 0975-8887
%V 96
%N 11
%P 44-51
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper enumerates the design of low power and high speed double edge triggered True Single Phase Clocking (TSPC) D- flip-flop. The TSPC CMOS flip-flop uses only one clock signal that is never inverted and it eliminates the clock skew. The originally developed TSPC flip-flop are very sensitive to the clock slope and large portion of power is spent in pre-charging the internal nodes, which makes TSPC dynamic circuits less power efficient. In the conventional CMOS design, high leakage current is becoming a significant contributor to power dissipation. To overcome the existing problem of CMOS TSPC D flip-flop, a Multi-threshold CMOS (MTCMOS) technology is used for leakage minimization. The designed flip-flops are compared in terms of power consumption and propagation delay and power delay product and simulations are carried out by MICROWIND 3. 1 tools. The proposed MTCMOS designs such as original MTCMOS implmentation and NMOS insertion in MTCMOS design of TSPC D flip-flop saves static power 57. 517% and 58. 871% as compared to conventional DE-TSPC D flip-flop respectively at 1. 2V.

References
  1. S. Unger and C. Tang, "Clocking Schemes for Very High-Speed Digital Systems", IEEE Transaction on Computers, Vol. : C-35, pp. 880-895, October 1986.
  2. M. Pedram, "Power minimization in IC Design: Principles and applications," ACM Transactions on Design Automation of Electronic Systems, Vol. 1, pp. 3-56, January 1996.
  3. B. Nikolic, "Design in The Power Limited Scaling Regime," IEEE Transaction on Electronic Devices, Vol. 55, No. 1, pp. 71-83, January 2008.
  4. Neil H. E. Weste, David Harris, Ayan Banerjee, CMOS VLSI DESIGN: A Circuits and Systems Prespective, Third Edition, pp. 129-131, 2009.
  5. S. Tahmasbi Oskuii, A. Alvandpour, "Comparative Study on Low-Power High- Performance Standard- Cell Flip- Flops", Microelectronics: Design, Technology, and Packaging, in Proceedings of the International Society for Optics and Photonics (SPIE), Vol. 5274, pp. 390-398, 2004.
  6. Surya Naik and Rajeevan Chandel, "Design of a Low Power Flip-Flop Using CMOS Deep Submicron Technology", IEEE, International Conference on Recent Trends in Information, Telecommunication and Computing (ITC), pp. 253-256, 2010.
  7. Neil H. E. Weste, David Harris, Ayan Banerjee, a book on "CMOS VLSI Design a Circuits and Systems Perspective", Pearson Education, 3rd Edition, pp. 275-275, 2009.
  8. J. A. Butts and G. S. Sohi, "A Static Power Model for Architects", IEEE, In Proceedings of the 33rd Annual International Symposium on Micro-architecture, pp. 191-201, 2000.
  9. J. S. Wang, "A New True-Single-Phase-Clocked Double Edge Triggered Flip-Flop for Low-Power VLSI Design", in Proceedings of IEEE International Symposium on Circuit and Systems, pp. 1896-1899, 12 June 1997.
  10. M Afghahi and C. Svenson, "A Unified Single Phase Clocking Scheme for VLSI Systems", IEEE Journal Solid-State and Circuits, Vol. 25, pp. 255-233, February 1990.
  11. B. Pontikakis and M. Nekhili. "A New Area Efficient Split- Output TSPC CMOS Latch for High Speed VLSI Applications", IEEE, International Conference of Microelectronics (ICM), pp. 101-104, 2002.
  12. L. Wei, Z. Chen, M. Johnson, K. Roy and V. De, "Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 16 – 24, March 1999.
  13. S. Mutoh et al. , "A 1V Multi-Threshold Voltage CMOS DSP with an Efficient Power Management Technique for Mobile Phone Application", IEEE Journal of Solid-State Circuits, Vol. 31, No. 11, pp. 1795–1802, 1996.
  14. Etienne Sicard, Sonia Ben Dhia, Syed Mahfuzul Aziz, "Teaching CMOS Circuit Desig in Nano-scale Technologies Using MICROWIND", Proceedings of the European workshop on microelectronics education, pp. 78-83, May 2010.
  15. Jayanth Srinivasan, "An Overview of Static Power Dissipation", CiteSeer public search engine and digital libraries for scientific and academic papers in the fields of computer and information science, pp. 1-7, 30 August 2011.
Index Terms

Computer Science
Information Sciences

Keywords

DE-TSPC flip-flop MTCMOS power dissipation figure of merit (FOM) BSIM.

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