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An Efficient Full Adder Design using Different Logic Styles
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 98 - Number 21 |
| Year of Publication: 2014 |
| Authors: Nishan Singh, Mandeep Kaur, Amardeep Singh, Puneet Jain |
10.5120/17310-7786
|
Nishan Singh, Mandeep Kaur, Amardeep Singh, Puneet Jain . An Efficient Full Adder Design using Different Logic Styles. International Journal of Computer Applications. 98, 21 ( July 2014), 38-41. DOI=10.5120/17310-7786
Abstract
The paper discusses a comparative study of full adders with various logic style of designing. Logic style affects the switching capacitance, transition activity, short circuit current and delay. Various logic styles have been compared taking full adder as a reference circuit and power dissipation and delay as reference parameters. Simulation results of all the full adders at technologies of 180nm, 90nm, 45nm of CMOS process have been provided. It is observed that less power is consumed in the Transmission based full adder than the Convention full adder and Pass Transistor full adder.
References
- N. Weste and K. Eshragian, Principles of CMOS VLSI Design: A Systems Perspective, Reading, MA: Addison Wesley, 1988, pp 231-237.
- Vojin G. Oklobdzija, "Simple and Efficient Circuit for Fast VLSI Adder Realization," IEEE International Symposium on Circuits and Systems Proceedings, 1988, pp. 1-4.
- Mokoto Suzuki, Norio Ohkubo, Toshinobu Yamanaka, Akihiro Shimuzu, Katsuro Sasaki, Yoshinobu Nakagome, "A 1. 5ns 32-bit CMOS ALU in Double Pass Transistor Logic," IEEE Journal of Solid State Circuits, November 1993, Vol. 28, No. 11,pp. 90-91.
- Mark Horowitz, Thomas Indermaur and Ricardo Gonzalez, "Low Power Digital Design," IEEE Journal of Solid State Circuits, Vol. 27 , 1994, pp. 473-487.
- Chetana Nagendra , Mary Jane Irwin and Robert Owens, "Area-Time-Power Tradeoffs in Parallel Adders," IEEE Transactions on Circuits and Systems, Vol. 43, Oct. 1996.
- Hanho Lee and Gerald E. Sobelman, "A new Low Voltage Full Adder Circuit", IEEE J. Solid State Circuits, Vol. 32,Jan 1997, pp. 114-118.
- Vojin G. Oklobdzija, "Differential and Pass Transistor CMOS Logic for High Performance Systems," Proc. 21st International Conference on Microelectronics, Vol. 2, Sep 1997, pp. 679-688.
- Reto Zimmermannn and Wolfgang Fichtner, "Low Power Logic Styles: CMOS versus Pass Transistor Logic," IEEE Journal on Solid State Circuits, Vol. 32, July 1997, pp. 1079-1090.
- Ahmed M. Shams and Magdy A Bayoumi, "A new Full Adder Cell For Low Power Applications", GLSVLSI, Great Lakes Symposium on VLSI'98, 1998, pp. 45.
- Damu Radhakrishnan, "A new low power CMOS full adder", IEE Electronic Letters, Vol. 35, No. 21, October 1999, pp. 1792-1794.
- Tudor Vinereanu and Sverre Lidholm, "An Improved Pass Transistor Synthesis Method for Low Power, High Speed CMOS Circuits," Proceeding of the 2000 International Symposium on Low Power Electronics and Design, pp. 120-124.
- Bhaskar Chatterjee, Manoj Sachdev and Ram Krishnamurthy, "A CPL-based Dual Supply 32-bit ALU for Sub 180nm CMOS Technologies," Proceedings of the 2004 International Symposium on Low Power Electronics and Design,2004, pp. 248-251.
- Singh, Balwinder, Rajneesh Goyal, Rakesh Kumar, and R. Singh. "Design and VLSI implementation of fuzzy logic controller. " IJCNS) International Journal of Computer and Network Security 1, no. 3 (2009).
- Hanan A. Mahmoud and Magdy A. Bayoumi , "A 10 transistor Low Power high speed full adder cell ", Journal of VLSI Signal Processing Systems,Vol. 2,Issue1,Jan2006,pp. 21-33.
- Sohan Purohit, Martin Margala, Macro Lanuza and Pasquale Corsonello, "New Performance/Power/ Area Efficient, Reliable Full Adder Design", GLSVLSI'09, ACM May,2009.
- SubodhWairya, Rajendra Kumar Nagaria, and Sudarshan Tiwari, " Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design", Hindawi Publishing Corporation VLSI Design Volume 2012.
- Saini, Vijender, Balwinder Singh, and Rekha Devi. "Area Optimization of FIR Filter and its Implementation on FPGA. " International Journal of Recent Trends in Engineering 1. 4 (2009).
- Mariano Aguirre-Hernandez and Monico Linares-randa," CMOS Full-Adders for Energy-Efficient Arithmetic Applications", IEEE transactions on very large scale integration (vlsi) systems, vol. 19, no. 4, april 2011, Pp. 718-721.
- Devi, Padma, Ashima Girdher, and Balwinder Singh. "Improved carry select adder with reduced area and low power consumption. " International Journal of Computer Applications 3. 4 (2010): 14-18.
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