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Reseach Article

Body Biasing Scheme to Control Leakage, Speed and Stability in SRAM Cell Design

Published on June 2015 by Rohit Lorenzo, Saurabh Chaudhury
International Conference on Computing, Communication and Sensor Network
Foundation of Computer Science USA
CCSN2014 - Number 1
June 2015
Authors: Rohit Lorenzo, Saurabh Chaudhury
ee685a35-d594-47fb-87bf-d362a12f7e2c

Rohit Lorenzo, Saurabh Chaudhury . Body Biasing Scheme to Control Leakage, Speed and Stability in SRAM Cell Design. International Conference on Computing, Communication and Sensor Network. CCSN2014, 1 (June 2015), 11-15.

@article{
author = { Rohit Lorenzo, Saurabh Chaudhury },
title = { Body Biasing Scheme to Control Leakage, Speed and Stability in SRAM Cell Design },
journal = { International Conference on Computing, Communication and Sensor Network },
issue_date = { June 2015 },
volume = { CCSN2014 },
number = { 1 },
month = { June },
year = { 2015 },
issn = 0975-8887,
pages = { 11-15 },
numpages = 5,
url = { /proceedings/ccsn2014/number1/21417-5003/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Computing, Communication and Sensor Network
%A Rohit Lorenzo
%A Saurabh Chaudhury
%T Body Biasing Scheme to Control Leakage, Speed and Stability in SRAM Cell Design
%J International Conference on Computing, Communication and Sensor Network
%@ 0975-8887
%V CCSN2014
%N 1
%P 11-15
%D 2015
%I International Journal of Computer Applications
Abstract

In this paper a new SRAM cell is designed with a body bias controller to control leakage, speed and stability. A novel controller circuit is proposed to control the value of threshold voltage. Operation of the proposed controller is based on word line signal levels. In order to reduce sub threshold leakage current, the NMOS access and driver transistor is adjusted to a higher threshold voltage. Similarly, threshold voltage of NMOS access transistor is adjusted to a low value for improved read and writes speed. As compared to conventional 6T SRAM cell, the proposed design reduces the leakage power by about 52. 27%, when tested on (8×16) SRAM cells.

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Index Terms

Computer Science
Information Sciences

Keywords

Leakage Power Dissipation Sub Threshold Current Power Gating Sleep Transistor And Transistor Stacking