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Reseach Article

Design of 16-bit Vedic Multiplier for Convolutional Encoder using VHDL

Published on August 2017 by Bhagyashree. V. Dagamwar, R. N. Mandavgane, D. M. Khatri
International Conference on Quality Up-gradation in Engineering Science and Technology
Foundation of Computer Science USA
ICQUEST2016 - Number 2
August 2017
Authors: Bhagyashree. V. Dagamwar, R. N. Mandavgane, D. M. Khatri
9231fe0e-3262-4d44-87f4-c521ec1dd8c6

Bhagyashree. V. Dagamwar, R. N. Mandavgane, D. M. Khatri . Design of 16-bit Vedic Multiplier for Convolutional Encoder using VHDL. International Conference on Quality Up-gradation in Engineering Science and Technology. ICQUEST2016, 2 (August 2017), 12-16.

@article{
author = { Bhagyashree. V. Dagamwar, R. N. Mandavgane, D. M. Khatri },
title = { Design of 16-bit Vedic Multiplier for Convolutional Encoder using VHDL },
journal = { International Conference on Quality Up-gradation in Engineering Science and Technology },
issue_date = { August 2017 },
volume = { ICQUEST2016 },
number = { 2 },
month = { August },
year = { 2017 },
issn = 0975-8887,
pages = { 12-16 },
numpages = 5,
url = { /proceedings/icquest2016/number2/28134-1669/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Quality Up-gradation in Engineering Science and Technology
%A Bhagyashree. V. Dagamwar
%A R. N. Mandavgane
%A D. M. Khatri
%T Design of 16-bit Vedic Multiplier for Convolutional Encoder using VHDL
%J International Conference on Quality Up-gradation in Engineering Science and Technology
%@ 0975-8887
%V ICQUEST2016
%N 2
%P 12-16
%D 2017
%I International Journal of Computer Applications
Abstract

In general, multiplication plays an vital role in the development of processors, DSP applications, image processing etc. So, designing of high speed multiplier is a neccesary choice. In this research, design of 4, 8 and 16-bit multiplier based on vedic mathematics has been presented. These multipliers further will be used in the design of convolutional encoder. Here, Urdhava Tiryakbhyam sutra is used for multiplication. It eliminates unwanted multiplication steps and follows a fast multiplication process and achieves a significantly less computation complexity over its conventional counterparts. All the modules are coded in VHDL and simulation done in Xilinx ISE 14. 5i.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Convolution Encoder Multiplier Urdhava Tiryakbhyam Vedic Mathematics