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Energy-Efficient CMOS Full Adder for Arithmetic Applications

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IJCA Proceedings on National Conference on Innovative Paradigms in Engineering & Technology 2013
© 2013 by IJCA Journal
NCIPET2013 - Number 8
Year of Publication: 2013
Authors:
Kiran Barapatre
P. J. Suryawanshi
Sanket Lichade

Kiran Barapatre, P J Suryawanshi and Sanket Lichade. Article: Energy-Efficient CMOS Full Adder for Arithmetic Applications. IJCA Proceedings on National Conference on Innovative Paradigms in Engineering & Technology 2013 NCIPET 2013(8):1-3, December 2013. Full text available. BibTeX

@article{key:article,
	author = {Kiran Barapatre and P. J. Suryawanshi and Sanket Lichade},
	title = {Article: Energy-Efficient CMOS Full Adder for Arithmetic Applications},
	journal = {IJCA Proceedings on National Conference on Innovative Paradigms in Engineering & Technology 2013},
	year = {2013},
	volume = {NCIPET 2013},
	number = {8},
	pages = {1-3},
	month = {December},
	note = {Full text available}
}

Abstract

In this paper, we present Energy efficient CMOS full adder, which is one of the basic building blocks of a modern electronic systems design. Energy-Efficiency is one of the most required features in digital electronic systems for high-performance and/or portable applications which signify PDP, it measures the energy consumed per switching event. This paper shows that complementary CMOS is the logic style of choice for the implementation of combinational circuits, if low voltage, low power, and small power-delay products are of concern with relatively low area.

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