Computer architecture researchers evaluate key areas such as pipelining, organization, instruction issue, branching, and exception handling when considering asynchronous and synchronous design and implementation trade-offs. Asynchronous or clockless designs are considered as an alternative to conventional synchronous digital system design. The major advantages of asynchronous are low power consumption, better modularity, higher robustness and higher speed. Virtually all processors are synchronous which are based on internal timing devices / circuits that regulate processing. As system becomes increasingly large and complex, this timing device a clock can cause big problems with clock skew and timing delay can create havoc with the overall design. It can also increase the circuit silicon and power dissipation. To overcome above limitations asynchronous design is considered aggressively. Each subsystems or functional blocks may be optimized without being synchronized to a global clock that may simplify interfacing. Thus the performance of the asynchronous system exhibits the average performance of the overall subsystems or functional block. Furthermore, asynchronous processors may yet prove to offer reduced power dissipation by inherently shutting down unused portions of the circuit.

1. A. J. Martin et al, "Asynchronous Techniques for System on Chip Design," in Proceedings of IEEE, vol. 94, no. 6, June 2006, pp 1089 - 1120.
2. G. M. Jacobs et al, "A Fully Asynchronous Digital Signal Processor using Self Timed Circuits," in IEEE Journal of Solid State Circuits, vol. 25, no. 6, Dec. 1990, pp 1526 - 1537.
3. T. H. Y. Meng, et al, "Asynchronous Design for Programmable Digital Signal Processors," in IEEE Transaction on Signal Processing, vol 39, no. 4, April 1999, pp 939 - 952.
4. T. H. Y. Meng, et al, "Asynchronous Processor Design for Digital Signal Processing," in IEEE International Conference on Acoustic, Speech and Signal Processing, 1988, pp 2013 - 2016.
5. K. Y. Yun, et al, "High Performance Asynchronous Pipeline Circuits," in IEEE International Symposium on Advance Research in Asynchronous Circuits and Systems, 1996, pp 17 - 28.
6. L. S. Neilsen, et al, "A Low Power Asynchronous Data Path for FIR Filter Bank," in IEEE International Symposium on Advance Research in Asynchronous Circuits and Systems, 1996, pp 197 - 207.
7. C. J. Elston et al, "Hades Towards The Design of an Asynchronous Superscalar Processor, "in IEEE Conference on Asynchronous Design Methodologies, 1995, pp 200 – 209.
8. R. Payne, "Asynchronous FPGA Architecture," in IEEProceedings of Compute Digit Technology, vol. 143, no. 5, Sep. 1996, pp 282 – 286.
9. W. H. F. J. Korver et al, "Asynchronous Implementation of the SCPP-A Counter flow Pipeline Processor," in IEEProceedings of Compute Digit Technology, vol. 143, no. 5, Sep. 1996, pp 287 – 294.
10. Alex Semenov et al, "Designing an Asynchronous Processor using Petri Nets," in IEEE Micro, April 1997, pp 54 – 64.
11. Martin Benes et al, "A High Speed Asynchronous Decompression Circuits for Embedded Processor," in 7thIEEE Conference in Advance Research in VLSI, 1997, pp 219 – 236.
12. Tony Werner et al, "Asynchronous Processor Survey," in IEEE Computer, Nov. 1997, pp 67 – 78.
13. K. T. Christensen et al, "The Design of an Asynchronous TinyRISC TR4101 Microprocessor Core," in IEEE International Symposium on Advance Research in Asynchronous Circuits and Systems, 1998, pp 108 - 119.
14. C. Ortega, et al, "Static Power Reduction Techniques for Asynchronous Circuits," in IEEE International Symposium on Asynchronous Circuits and Systems, 2010, pp 52 - 61.
15. Clinton Kelly et al, "SNAP A Sensor Network Asynchronous Processor," in IEEE International Symposium on Asynchronous Circuits and Systems, 2003, pp 24 - 33.
16. C. LaFrieda, et al, "Reducing Power Consumption with Relaxed Quasi Delay Insensitive Circuits," in IEEE International Symposium on Asynchronous Circuits and Systems, 2009, pp 217 - 226.
17. RanjitManohar, "Reconfigurable Asynchronous Logic," in IEEE International Custom Integrated Circuits Conference, 2006, pp 13 - 20.
18. M. Hirayama, "VLSI Oriented Asynchronous Architecture," in 13th IEEE International Symposium on Computer Architecture, 1986, pp 290 – 296.
19. B. R. Sheikh, et al, "An Operand Optimized Asynchronous IEEE 754 Double Precision Floating Point Adder," in IEEE International Symposium on Asynchronous Circuits and Systems, 2010, pp 151 - 162.
20. Mika Nystrom et al, "A pipelined Asynchronous Cache System," in Caltech Technical Report, 2003, pp 1 – 10
21. Y. Liu et al, "Designing an Asynchronous FPGA Processor for Low Power Sensor Network," in IEEE International Symposium on Signals, Circuits and Systems, 2009, pp 261 – 266.
22. T. N. Prabakar, et al, "FPGA Based Asynchronous Pipelined Multiplier with Intelligent Delay Controller," in IEEE International SoC Design Conference, 2008, pp 304 – 309.
23. BabakRahbaran, et al, "Is Asynchronous Logic More Robust Then Synchronous Logic," in IEEE Transaction on Dependable and Secure Computing, vol. 6, no. 4, Dec. 2009, pp 282 – 294.
24. Nikoloas Minas et al, "FPGA Implementation of an Asynchronous Processor with Online and Offline Testing Capabilities," in 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008, pp 128 – 137.
25. J. L. Yang, et al, "A Case Study on Asynchronous VLSI Design Platform," in IEEE Conference on Electron Devices and Solid state Circuits, 2007, pp 1167 – 1170.
26. ViranthaEkanayake et al, "An Ultra Low Power Processor for Sensor Network," in Proceedings of 11th International Conference on Architectural Support for Programming Languages & Operating systems, 2004, pp 27 – 36.
27. M. Marshall et al, "A Low Power Information Redundant Concurrent Error Detecting Asynchronous Processor," in 10thEuromicro Conference on Digital System Design Architecture, Methods and Tools, 2007.
28. Martin Simlastic, et al, "Clockless Implementation of LEON2 for Low Power Applications," in IEEE Conference on Design and Diagnostics of Electronic Circuits and Systems, 2007, pp 1 - 4.
29. H. R. Gerber, et al, "Design of an Asynchronous Microprocessor using RSFQ-AT," in IEEE Transaction on Applied Superconductivity, vol. 17, no. 2, June 2007, pp 490 – 493.
30. HarriLampinen et al, "Design of Scalable Asynchronous Dataflow Processor," in IEEE Conference on Design and Diagnostics of Electronic Circuits and Systems, 2006, pp 85 – 86.
31. JianGao et al, "A Novel Asynchronous Multiply Function Multiply Accumulator," in 6th IEEE International Conference on ASICs, 2005, pp 223 – 226.
32. L. Necchi et al, "An Ultra Low Energy Asynchronous Processor For Wireless Sensor Networks," in 12th IEEE International Symposium on Asynchronous Circuits and Systems, 2006, pp 1 - 8.
33. X. Lao et al, "Low Overhead Asynchronous RISC Microprocessor A Design Experiment," in 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004, pp 377 – 380.
34. P. D. Hyde et al, "A Comparative Study of the Design of Synchronous and Asynchronous Self Checking RISC Processor," in 10th IEEE International Online Testing Symposium, 2004.
35. Y. W. Li et al, "High Throughput Asynchronous Datapath with Software Controlled Voltage Scaling," in IEEE Journal of Solid State Circuits, vol. 39, no. 4, April 2004, pp 704 – 709.
36. V. S. P. Rakapa et al, "A Mixed Clock Issue Queue Design for Gobally Asynchronous Locally Synchronous Processor Cores," in International Symposium on Low Power Electronics and Design, Aug. 2003, pp 372 – 377.
37. J. H. Lee et al, "A Novel Asynchronous Pipeline Architecture for CISC Type Embedded Controller, A8051," in 45th Midwest Symposium on Circuits and Systems, 2002, vol. 2, pp 675 – 679.
38. Puah W. B. et al, "Rapid Prototyping Asynchronous Processor," in IEEE International Conference on Semiconductor Electronics, 2000, pp 223 – 228.
39. K. S. Stevens et al, "An Asynchronous Instruction Length Decoder," in IEEE Journal of Solid state Circuits, vol. 36, no. 2, Feb. 2001, pp 217 – 228.
40. S. B. Furber et al, "AMULET 2e An Asynchronous Embedded Controller," in Proceedings of the IEEE, vol. 87, no. 2, Feb. 1999, pp 243 – 256.
41. Clive Max Maxfield, "The Design Warrior's Guide to FPGAs," Elsevier Publication, 2006.
42. S. M. Kang et al, "CMOS Digital Integrated Circuits," Tata McGraw Hill Edition, 3rd Edition, 2003.
43. D. L. Perry, "VHDL Programming by Examples," Tata McGraw Hill Edition, 4th Edition, 2002.
44. J. Bhasker, "A VHDL Primer," Pearson Education, 3rd Edition, 2000.
45. J. Bhasker, "Synthesis Primer," Pearson Education, 2001.
46. R. P. Jain, "Modern Digital Electronics," Tata McGraw Hill Edition, 4th Edition, 2010.
47. Stephen Brown, "Fundamentals of Digital Logic Design with VHDL, Tata McGraw Hill Edition, 2nd Edition, 2007.
48. Neil H. E. Weste et al, "CMOS VLSI Design," Pearson Education, 3rd Edition, 2006.
49. J. M. Yarbrough, "Digital Logic Applications and Design," Thomson Learning, 2001.
50. D. P. Leach et al, "Digital Principles and Applications," Tata McGraw Hill Edition, 5th Edition, 2002.
51. R. J. Baker et al, "CMOS Circuit Design, Layout and Simulation," IEEE Press Series on Microelectronic System, 1998.
52. J. M. Rabaey et al, "Digital Integrated Circuits A Design Perspective," Tata McGraw Hill Edition, 2nd Edition, 2002.
53. Holger Karl et al, "Protocols and Architecture for Wireless Sensor Networks," John Wiley and sons, 2005.
54. K. A. Fawaz et al, "A Dynamically Reconfigurable Asynchronous Processor," in IEEE Symposium on Application Specific Processor, 2010, pp 93 – 96.
55. Taylor S et al, "Asynchronous Data Driven Circuit Synthesis," in IEEE Transaction on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 7, 2010, pp 1093 – 1106.
56. Rossi D et al, "A Heterogenous Digital Signal Processor for Dynamically Reconfigurable Computing, in IEEE Journal of Solid State Circuits, vol. 45, no. 8, 2010, pp 1615 – 1626.

Asynchronous Design Low Power Consumption Wireless Sensor Node.