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Reseach Article

Design of Low Power FlipFlop to Reduce Area and Delay using Conditional Pulse Enhancement Method

Published on November 2012 by G. Venkadeshkumar, K. Pandiaraj
International Conference on Electronics, Communication and Information systems
Foundation of Computer Science USA
ICECI - Number 2
November 2012
Authors: G. Venkadeshkumar, K. Pandiaraj
8a550638-0089-4020-9e24-196d002f786b

G. Venkadeshkumar, K. Pandiaraj . Design of Low Power FlipFlop to Reduce Area and Delay using Conditional Pulse Enhancement Method. International Conference on Electronics, Communication and Information systems. ICECI, 2 (November 2012), 25-28.

@article{
author = { G. Venkadeshkumar, K. Pandiaraj },
title = { Design of Low Power FlipFlop to Reduce Area and Delay using Conditional Pulse Enhancement Method },
journal = { International Conference on Electronics, Communication and Information systems },
issue_date = { November 2012 },
volume = { ICECI },
number = { 2 },
month = { November },
year = { 2012 },
issn = 0975-8887,
pages = { 25-28 },
numpages = 4,
url = { /specialissues/iceci/number2/9470-1018/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Special Issue Article
%1 International Conference on Electronics, Communication and Information systems
%A G. Venkadeshkumar
%A K. Pandiaraj
%T Design of Low Power FlipFlop to Reduce Area and Delay using Conditional Pulse Enhancement Method
%J International Conference on Electronics, Communication and Information systems
%@ 0975-8887
%V ICECI
%N 2
%P 25-28
%D 2012
%I International Journal of Computer Applications
Abstract

A low power pulse triggered ?ip?op (P-FF) design is done by the pulse generation control logic, an AND function, is removed from the critical path to facilitate a faster discharge operation. A simple two-transistor AND gate design is used to reduce the circuit complexity. A conditional pulse enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse generation circuit can be reduced for power saving. Various post layout simulation results based on UMC CMOS 90-nm technology reveal that the enhanced pulse triggered FF design features the best power-delay-product performance in seven FF designs under comparison. Its maximum power saving against rival designs is up to 38. 4%. Compared with the conventional transmission gate based flipflop design. The average leakage power consumption is also reduced by a factor of 3. 52.

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Index Terms

Computer Science
Information Sciences

Keywords

Flip?op Low Power Pulse Triggered