Implementation of on Chip Data Bus Using Pre Emphasis Signaling

Print
 
Download Full Text
IJCA Special Issue on Optimization and On-chip Communication
© 2012 by IJCA Journal
ooc - Number 1
Year of Publication: 2012
Authors:
Pallavi Dedge
S.C. Badwaik

Pallavi Dedge and S C Badwaik. Article: Implementation of on Chip Data Bus Using Pre Emphasis Signaling. IJCA Special Issue on Optimization and On-chip Communication ooc(1):32-39, February 2012. Full text available. BibTeX

@article{key:article,
	author = {Pallavi Dedge and S.C. Badwaik},
	title = {Article: Implementation of on Chip Data Bus Using Pre Emphasis Signaling},
	journal = {IJCA Special Issue on Optimization and On-chip Communication},
	year = {2012},
	volume = {ooc},
	number = {1},
	pages = {32-39},
	month = {February},
	note = {Full text available}
}

Abstract

This work describes a differential current-mode bus architecture based on driver pre-emphasis for on-chip global interconnects that achieves high-data rates while reducing bus power dissipation and improving signal delay latency. The 16-b bus core fabricated in 0.25- ? m complementary metal–oxide–semi- conductor (CMOS) technology attains an aggregate signaling data rate of 64 Gb/s over 5–10-mm-long lossy interconnects. With a supply of 2.5 V, 25.5–48.7-mW power dissipation

References

  • H. Bakoglu, “Circuits,” in Interconnections and Packaging for VLSI,1st ed. Reading, MA: Addison-Wesley, 1990.
  • P. Larsson-Edefors, “Investigation on maximal throughput of a CMOS repeater chain,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl.,vol. 47, no. 4, pp. 602–606, Apr. 2000
  • R. Chang, N. Talwalkar, C. Yue, and S. Wong, “Near speed-of-ling signaling over on-chip electrical interconnects,” IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 834–838, May 2003.
  • P. Jose and K. L. Shepard, “Distributed loss compensation for lowlatency on-chip interconnects,” in IEEE ISSCC Dig. Tech. Papers, Feb.2006, vol. 21.7, pp. 1558–156
  • E. Prete, D. Scheideler, and A. Sanders, “A 100 mW 9.6 Gb/s transceiver in 90 nm CMOS for next-generation memory interfaces,”in IEEE ISSCC Dig. Tech. Papers, , Feb. 2006, vol. 4.5, pp.253–262.
  • R. Bashirullah, W. Liu, R. Cavin, III, and D. Edwards, “A 16 Gb/s adaptive banwidth on-chip bus based on hybrid current/voltage mode signaling,” IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 461–473,Feb. 2006.
  • N. Tzartzanis and W. W. Walker, “Differential current-mode sensingfor ef?cient on-chip global signaling,” IEEE J. Solid-State Circuits, vol.40, no. 11, pp. 2141–2147, Nov.2005.
  • D. Schinkel, E. Mensink, E. A. M. Klumperink, E. van Tuijl, and B.Nauta, “A 3-Gb/s/ch transceiver for 10-mm uninterrupted RC-limited on-chip interconnects,” IEEE J. Solid-State Circuits, vol. 41, no. 1, pp.297–306, Jan. 2006.
  • L. Zhang, J. Wilson, R. Bashirullah, L. Luo, J. Xu, and P. Franzon, “A 32 Gb/s on-chip bus with driver pre-emphasis signaling,” in Proc. IEEE Custom Integr. Circuits Conf., Sep. 2006, vol. P.16, pp. 265–268.
  • W. Dally and J. Poulton, Digital Systems Engineering.Cambridge,U.K.:CambridgeUniv.Press, 1997.
  • T. Sakurai, “Closed-form expressions for interconnection delay, coupling,and crosstalk in VLSI’s,” IEEE Trans. Electron Devices, vol. 40,no. 1, pp. 118–124, Jan. 1993.
  • E. Seevinck, P. van Beers, and H. Ontrop, “Current-mode techniques for high-speed VLSI circuits with application to current sense ampli?er for CMOS SRAM’s,” IEEE J. Solid-State Circuits, vol. 26, no. 4, pp. 525–536, Apr. 1991.
  • L. Zhang, J. Wilson, R. Bashirullah, and P. Franzon, “Differential current-mode signaling for robust and power ef?cient on-chip global interconnects,”Electr. Perform. Electron. Packag., pp. 315–318, Oct. 2005.
  • B. Nikolic, V. Stojanovic, V. G. Oklobdzija, W. Jia, J. Chiu, and M.Leung,“Improved sense-ampli?er-based ?ip-?op: Design and measurements,”IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 876–884,Jun. 2000.
  • R. Ho, K. Mai, and M. Horowitz, “Ef?cient on-chip global interconnects,” in Proc. Symp. Very Large Scale Integr. Circuits, Jun. 2003, pp. 271–274.
  • K. Banerjee and A. Mehrotra, “A power-optimal repeater insertion methodology for global interconnects in nanometer designs,” IEEE Trans. Electron Devices, vol. 49, no. 11, pp. 2001–2007, Nov. 2002.
  • Y. Ismail, E. Friedman, and J. Neves, “Figureures of merit to characterize the importance of on-chip inductance,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 7, no. 6, pp. 442–449, Dec. 199
  • A. Deutsch, P. W. Coteus, G. V. Kopcsay, H. H. Smith, C. W. Surovic, B. L. Krauter, D. C. Edelstein, and P. J. Restle, “On-chip wiring design challenges for gigahertz operation,” Proc. IEEE, vol. 89, no. 4, pp. 529–555, Apr. 2001
  • D. Burger and T. M. Austin, The SimpleScalar Tool Set, Version 2.0,Univ. Wisconsin, Madison, WI, Tech. Rep. CS-TR-97-1342, Jun. 1997.
  • J. M. Rabaey, Digital Integrated Circuits: A Design Perspective. Englewood
  • Cliffs, NJ: Prentice-Hall, 1996.
  • United State Patent (Number:7557630,b2,7 july 2009) Name: sense amplifier based flip flop for reducing output delay and method thereof.