Vedic multiplier is based on ancient Indian Vedic mathematics that offers simpler and hierarchical structure. Multi-valued logic results in the effective utilization of interconnections, which reduces the chip size and delay. This paper proposes that if the potential of multi-valued logic is combined with simplicity of Vedic architecture, it may result in an efficient multiplier design. Since the performance of a digital signal processor depends mainly on the multipliers used, the proposed approach can greatly enhance the performance of a digital signal processor.

1. Jagadguru Swami Sri Bharati Krishna Tirthji Maharaja, "Vedic Mathematics", Motilal Banarsidas Publication, 1986
2. Sumit R. Vaidya, "Design of High Performance 8x8-bit Multiplier Based on Vedic Mathematics in ASIC", Dissertation for M. Tech. Project, BDCOE, RTM Nagpur University, January 2011
3. Kunchigi V. , Kulkarni L. and Kulkarni S. , "High Speed And Area Efficient Vedic Multiplier", International Conference on Devices, Circuits and Systems, pp. 360-364, March 2012
4. Jai Tripathi, Priya Tripathi, Deepti Tripathi, "An Efficient Design of Vedic Multiplier using New Encoding Scheme", International Journal of Computer Applications, Vol. 53, No. 11, September 2012
5. Mehta P. and Gawali D. , "Conventional Versus Vedic Mathematical Method For Hardware Implementation of a Multiplier", International Conference on Advances in Computing, Control & Telecommunication Technologies, pp. 640-642, Dec. 2009
6. Harpreet Singh Dhillon and Abhijit Mitra, "A Reduced- Bit Multiplication Algorithm For Digital Arithmetics", International Journal of Computational and Mathematical Sciences, 2008
7. Keivan Navi, Sahar Daraeizadeh, Babak Mazloom Nejad and Majid Haghparast, "A Novel Current Mode Full Adder Based on Majority Function", World Applied Sciences Journal 4(5), pp. 676-680, 2008
8. Bob Radanovic and Marek Syrzycki, "Current-Mode CMOS Adders Using Multiple-Valued Logic", Canadian Conference on Electrical and Computer Engineering, vol. 1, pp. 190-193, May 1996
9. Hirokatsu Shirahama and Takahiro Hanyu, "Design of High-Performance Quaternary Adders Based on Output-Generator Sharing", 38th International Symposium on Multiple-Valued Logic, pp. 8-13, May 2008
10. Carlos Roberto Mingoto Junior, "A Quaternary Logic Gate Using Current-Mode Operation With Bipolar Transistors Equivalent To An Exclusive-OR Binary Gate", Proc. of IEEE International Conference on Electronics Circuits and Systems, pp. 1-4, December 2005
11. Carlos Roberto Mingoto Junior, "A Quaternary Half-Adder Using Current-Mode Operation With Bipolar Transistors", Proc. of 36th International Symposium on Multiple-Valued Logic, 2006
12. Cini U. and Morgul A. , "A Multi-Operand Adder Circuit Design Using Novel Multi-Valued Current Mode Design Technique", International Conference on Electrical and Electronics Engineering, pp. 49-53, Nov. 2009
13. Hanyu T. and Kameyama M. , "A 200 MHz Pipelined Multiplier Using 1. 5V Supply Multiple-Valued MOS Current Mode Circuits With Dual-Rail Source Coupled Logic", IEEE Journal of Solid-State Circuits, vol. 30, pp. 1239-1245, Nov. 1995
14. Clarke C. T. , Nudd G. R. and Summerfield S. , "Current Mode Techniques For Multiple Valued Arithmetic And Logic", IEEE International Symposium on Circuits and Systems, vol. 4, pp. 279-282, June 1994
15. Sheng Lin, Yong-Bin Kim and Lombardi F. , "CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits", IEEE Transactions on Nanotechnology, vol. 10, Issue: 2, pp. 217-225, March 2011
16. Vasundara Patel K S, K S Gurumurthy, "Design of High Performance Quaternary Adders", International Journal of Computer Theory and Engineering, Vol. 2, No. 6, December 2010
17. V. Varshavsky, I. Levin, V. Marakhovsky, A. Ruderman, N. Kravchenko, "Fuzzy Decision Diagram Realization By Analog CMOS Summing Amplifiers", Proc. of 11th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2004), Tel Aviv, pp. 286-289, December 2004
18. V. Varshavsky, V. Marakhovsky, I. Levin, H. Saito, "Multiple-valued Logic Approach to Fuzzy Controllers Implementation", WSEAS Transactions on Electronics, Issue 6, Volume 4, June 2007
19. Abhishek Gupta, "Arithmetic Unit Implementation Using Delay Optimized Vedic Multiplier with BIST Capability", International Journal of Engineering and Innovative Technology (IJEIT), Volume 1, Issue 5, May 2012
20. Sumit Vaidya and Deepak Dandekar, "Delay-Power Performance Comparison Of Multipliers In VLSI Circuit Design", International Journal of Computer Networks & Communications (IJCNC), Vol. 2, No. 4, July 2010
21. Alejandro F. Gonzalez and Pinaki Mazumder, "Redundant Arithmetic, Algorithms And Implementations", ELSEVIER INTEGRATION, The VLSI Journal 30, pp. 13-53, 2000
22. V. Varshavsky, V. Marakhovsky, I. Levin and N. Kravchenko, "Fuzzy Controller CMOS Implementation", WSEAS Transactions on Circuits and Systems, Issue 9, Vol. 3, pp. 1762-1769, Nov. 2004
23. V. Varshavsky, V. Marakhovsky and I. Levin, "CMOS Fuzzification Circuits for Linear Membership Functions", Proc. of 6th WSEAS International Conference on Fuzzy Systems, Portugal, pp132-137, June 2005

Current-mode Multi-valued Logic Vedic Multiplier Arithmetic Circuits Digital Signal Processing