The week's pick
Random Articles
Reseach Article
Impact of Negative Bias Temperature Instability on 6T CMOS SRAM Cell Performance
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 128 - Number 12 |
| Year of Publication: 2015 |
| Authors: Pallvi Rani, Gurmohan Singh, Manjit Kaur |
10.5120/ijca2015906678
|
Pallvi Rani, Gurmohan Singh, Manjit Kaur . Impact of Negative Bias Temperature Instability on 6T CMOS SRAM Cell Performance. International Journal of Computer Applications. 128, 12 ( October 2015), 1-6. DOI=10.5120/ijca2015906678
Abstract
This paper presents the effect of negative bias temperature instability (NBTI) on a 6T CMOS SRAM cell and a technique to correct the NBTI induced error. The effect of NBTI on the generation of interface traps and Ids-Vgs characteristics is analyzed. The degradation of static noise margin and PMOS transistor’s Vth with increase in simulation time is analyzed in SRAM cell. Threshold voltage degradation is simulated at two different technologies and it is found that NBTI degradation is prominent in lower technology nodes. As memories occupy the maximum area on a chip, thus, more robust SRAM design is required for high reliability of SRAM cell. MOSFET reliability analysis (MOSRA) model is used to simulate the effects of Bias Temperature Instability and hot carrier injection. Error introduced because of NBTI is corrected using a bit flipping technique.
References
- A. Haggag, G. Anderson, S. Parihar, D. Burnett, et al., “Understanding SRAM High-Temperature- Operating-Life NBTI: Statistics and Permanent Vs Recoverable Damage”, in Proc. IEEE International Reliability Physics Symposium, pp. 452-456, Apr. 2007.
- A. Carlson, “Mechanism of Increase in SRAM Vmin Due to Negative-Bias Temperature Instability”, IEEE Trans. on Device and Materials Reliability, vol. 7, no. 7, pp. 473-478, 2007.
- R. Kapre, K. Shakeri, H. Puchner, J. Tandigan, et al., “SRAM Variability and Supply Voltage Scaling Challenges”, in Proc. IEEE International ReliabilityPhysics Symposium, pp. 23-28, Apr. 2007.
- T. Kim, W. Zhang, and C. Kim, “An SRAM Reliability Test Macro for Fully-Automated Statistical Measurements of Vmin Degradation”, in Proc. IEEE Custom Integrated Circuits Conference, pp. 231-234, Sept. 2009
- Hong Luo, Yu Wang, Ku He, RongLuo, Huazhong Yang, Yuan Xie, “Modeling of PMOS NBTI Effect Considering Temperature Variation”, in Proc. 8th International Symposium on Quality Electronic Design, pp.139,144, 26-28 March 2007.
- Mostafa H., Anis M., Elmasry M., “Adaptive Body Bias for reducing the impacts of NBTI and process variations on 6T SRAM cells”, IEEE Trans. Circuits and Systems I: Regular Papers, vol.58, no.12, pp.2859-2871, December 2011
- K. K. Kim, W. Wang, and K. Choi, “On-chip aging sensor circuits for reliable nanometer MOSFET digital circuits” ,IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 10, pp. 798–802, Oct. 2010
- R. A. B. Devine, J.-L., Autran W. L., Warren K. L., Vanheusdan and J.-C. Rostaing, “Interfacial hardness enhancement in deuterium annealed 0.25μm n-channel metal oxide semiconductor transistors”, Applied Physics Letter, vol. 70, no. 22, pp. 2999-3001, June 1997.
- Sudheer Padala “New Model for Simulating Impact of Negative Bias Temperature Instability (NBTI) in CMOS Circuits”, Ph.D. dissertation, Arizona State University December 2014.
- Alam M.A., “A critical examination of the mechanics of dynamic NBTI for pMOSFETs,” IEDM Tech Dig, pp. 346–9, 2003.
- Md Ismail S., Hossain I., Hossain M.S., Arafat Y., “A faster approach to periodic data flipping of SRAM array for NBTI recovery”, in Proc. 16th International Conference on Computer and Information Technology (ICCIT), pp.448,454, 8-10 March 2014
- B. Raj, A. K. Saxena and S. Dasgupta, “Nanoscale FinFET Based SRAM Cell Design: Analysis of Performance metric, Process variation, Underlapped FinFET and Temperature effect” IEEE Circuits and System Magazine, vol. 11, issue 2, pp. 38- 50, 2011.
- Balwant Raj, Anita Suman, Gurmohan Singh, “Analysis of Power Dissipation in DRAM Cells Design for Nanoscale Memories”, International Journal of Information Technology & Knowledge Management, July-December 2009, Volume-2,No. 2,pp. 371-374.
- Karishma Bajaj, Manjit Kaur, Gurmohan Singh,” Design and Analysis of Hybrid CMOS SRAM Sense Amplifier, International Journal of Electronics and Computer Science Engineering, Volume-1, Number-2, pp. 718-726, 2012.
- MOS Device Aging Analysis with HSPICE and CustomSim,availableathyperlink:https://www.synopsys.com/Tools/Verification/AMSVerification/CircuitSimulation/HSPICE/Documents/mosra-wp.pdf.
Index Terms
Keywords