CFP last date
22 April 2024
Call for Paper
May Edition
IJCA solicits high quality original research papers for the upcoming May edition of the journal. The last date of research paper submission is 22 April 2024

Submit your paper
Know more
Reseach Article

Novel VLSI Architectures for Image Segmentation and Edge Detection Algorithm

by Prachi Dewan, Rekha Vig, Neeraj Shukla, B. K. Das
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 149 - Number 10
Year of Publication: 2016
Authors: Prachi Dewan, Rekha Vig, Neeraj Shukla, B. K. Das
10.5120/ijca2016911577

Prachi Dewan, Rekha Vig, Neeraj Shukla, B. K. Das . Novel VLSI Architectures for Image Segmentation and Edge Detection Algorithm. International Journal of Computer Applications. 149, 10 ( Sep 2016), 32-36. DOI=10.5120/ijca2016911577

@article{ 10.5120/ijca2016911577,
author = { Prachi Dewan, Rekha Vig, Neeraj Shukla, B. K. Das },
title = { Novel VLSI Architectures for Image Segmentation and Edge Detection Algorithm },
journal = { International Journal of Computer Applications },
issue_date = { Sep 2016 },
volume = { 149 },
number = { 10 },
month = { Sep },
year = { 2016 },
issn = { 0975-8887 },
pages = { 32-36 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume149/number10/26036-2016911577/ },
doi = { 10.5120/ijca2016911577 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:54:25.543226+05:30
%A Prachi Dewan
%A Rekha Vig
%A Neeraj Shukla
%A B. K. Das
%T Novel VLSI Architectures for Image Segmentation and Edge Detection Algorithm
%J International Journal of Computer Applications
%@ 0975-8887
%V 149
%N 10
%P 32-36
%D 2016
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Field programmable gate arrays (FPGA) are the devices which can be easily employed for image and video processing applications. FPGA implementation is always faster than any other digital signal processor due to its parallel image processing capabilities. This paper proposes the hardware co-simulation model of different traffic signs carried out using Xilinx System Generator tool. The proposed system uses image pre-processing, color conversion, thresholding and edge detection of still grayscale images taken from a distance of 50m. Experimental results show that hardware co-simulation was successful in SPARTAN-3E DSP xc6slx45-3csg324 development board operating at 100MHz system clock.

References
  1. J.C.Russ ”Image processing Handbook”, Sixth Edition, CRC Press, 2011.
  2. Masaharu Yamamoto, Anh-Tuan Hoang, Mutsumi Omori and Tetsushi Koide,“ Compact Hardware Oriented Number Recognition Algorithm for Real-Time Speed Traffic-Sign Recognition”, IEEE Transactions On Intelligent Transportation Systems, Vol. 13, No. 4, pp. 2535-2538, December 2015.
  3. Jack Greenhalgh and Majid Mirmehdi,”Real –Time Detection and Recognition of Road Traffic Signs”, IEEE Transactions of Intelligent Transportation System, Vol.13, No.4, pp. 1498-1505, December 2012.
  4. Yi Yang, Hengliang Luo, Huarong Xu and Fuchoa Wu,” Towards Real -Time Traffic Sign Detection and Classification”, IEEE International Conference on Intelligent Transportation Systems, pp. 87-92, Oct 2014.
  5. Jesmin F. Khan, Sharif M. A. Bhuiyan and Reza R.Adhami,” Image Segmentation and Shape Analysis for Road-Sign Detection”, IEEE Transactions On Intelligent Transportation Systems, Vol. 12, No. 1, pp .83-96, March 2011.
  6. Tam P, Cao Guang and Deng Darrell Elton,” Grayscale Image Segmentation for Real-time Traffic Sign Recognition: the Hardware Point of View”, SPIE Proceedings of Real- Time Image and Video Processing , Vol. 7244, Feb 2009.
  7. Nagarathna H S, Sushma P S and Ramesh Kumar K R,” Design and Simulation of Robot Vision System Using Simulink”, International Journal of Scientific & EngineeringResearch,Vol. 3, Issue 6, June 2012.
  8. Wei Liu, Yujie Liu, Hongfei Yu, Huai Yuan and Hong Zhao,” Real-Time Speed Limit Sign Detection and Recognition from Image Sequences”, IEEE International Conference on Artificial Intelligence and Computational Intelligence, pp. 262-267, 2010 .
  9. Dushyant Mankar, Prof. S.S.Mungona,” Low Level Image Processing Algorithms using hardware Software Co-Simulation,” IETE Mid Term Symposium on Impact of Technology of Skill Development, International Journal of Electronics, Communication & Soft Computing Science and Engineering, pp. 58-62.
  10. H.T. Panduranga ,Dr. Naveen Kumar and Sharath Kumar ,” Hardware Software Co-Simulation of the Multiple Image Encryption Technique Using the Xilinx System Generator,” Journal of Information Process System, Vol.9, No.3,.pp-499-510, September 2013.
  11. Luis Manuel Garcés Socarrás, Santiago Sanchez-Solano, Piedad Brox Jimenez and Alejandro José Cabrera Sarmiento,” Library for model-based design of image processing algorithms on FPGAs,” University of Antioquia, pp. 36-47. September 2013.
  12. Rihab Hmida, Abdessalem Ben Abdelali, Abdellatif Mtibaa,” Hardware implementation and validation of a traffic road sign detection and identification system”, Journal of real time image processing, Springer, March 2016.
  13. A. M. Sapkal, M. Munot and M. A. Joshi, “R' G'B' to Y'CbCr Color Space Conversion Using FPGA”,IET International Conference on Wireless,Mobile and Multimedia Network , pp.255 – 258, Jan. 2008.
  14. A. Møgelmose, M. M. Trivedi, and T. B. Moeslund, “Vision-based traffic sign detection and analysis for intelligent driver assistance systems: Perspectives and survey," IEEE Transactions on Intelligent System, Vol. 13, No. 4, pp. 1484-1497, December 2012.
  15. Mohammed Alareqi, R.Elgouri,A.Zemmouri, L.Hlou,” High-Level Design for Real Time Implementation of CSC Algorithm on FPGA using Matlab and Simulink Simulation”,Journal of Theoretical and Applied Information Technology Vol.84,No.1, February 2016.
  16. Documentation of Xilinx, User Guides. Xilinx System Generator for DSP Reference Guide,2010. http://www.xilinx.com/tools/sysgen.htm
  17. Yan Han and Erdal Oruklu,” Real-Time Traffic Sign Recognition Based on Zynq FPGA and ARM SoCs” , IEEE International Conference on Information Technology,pp. 373-376, 2014.
  18. Dr.Ush Rani .Nelakuditi, M.Naresh Babu, Mr.T.Narayana Bhagirath,” Efficient Real Time Hardware Co-Simulation for Image Enhancement Applications”, IEEE Sponsored Second International Conference On Electronics And Communication System,pp.1580-1583.
Index Terms

Computer Science
Information Sciences

Keywords

FPGA Hardware Co-Simulation Xilinx System Generator (XSG) Simulink.