The week's pick
Reseach Article
Efficient Reversible ALU based on Logic Gate Structure
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 150 - Number 2 |
| Year of Publication: 2016 |
| Authors: Aanchal Shukla, Minal Saxena |
10.5120/ijca2016911469
|
Aanchal Shukla, Minal Saxena . Efficient Reversible ALU based on Logic Gate Structure. International Journal of Computer Applications. 150, 2 ( Sep 2016), 32-36. DOI=10.5120/ijca2016911469
Abstract
Reversible circuits are like routine rationale circuits with the exception of that they are worked from reversible doors. In reversible entryways, there is a novel, balanced mapping between the inputs furthermore, yields, not the situation with customary rationale. Likewise, reversible doors require steady ancilla inputs for reconfiguration of door capacities and waste yields that assistance in keeping reversibility. In this paper we have implemented reversible arithmetic logic unit (RALU) consist of F, Fr, HNG and PAOG Gate. In this design consumed of 24 costs and 11 delays. In this design be calculate seven logical operations: ADD, SUB, OR, NOR, NOT, NAND and AND. All design is simulated in Xilinx 14.2i and synthesis result in different device family.
References
- M. Morrison and N. Ranganathan, "Design of a Reversible ALU Based on Novel Programmable Reversible Logic Gate Structures," IEEE International Symposium on VLSI, 2011, pp. 126-131.
- Mr. Abhishek Gupta, Mr. Utsav Malviya and Prof. Vinod Kapse, “Design of Speed, Energy and Power Efficient Reversible Logic Based Vedic ALU for Digital Processors”, 978-1-4799-4910-6/14 $31.00 © 2012 IEEE DOI 10.1109/ACCT.2014.70.
- Nidhi Gupta, “Thermal Analysis of Energy Efficient Clock Gated Arithmetic Logic Unit on FPGA”, 978-1-4799-4190-2/14/$31.00 ©2014 IEEE.
- Mr. Abhishek Gupta, Mr. Utsav Malviya and Prof. Vinod Kapse, “Design of Speed, Energy and Power Efficient Reversible Logic Based Vedic ALU for Digital Processors”, 978-1-4799-4910-6/14 $31.00 © 2012 IEEE DOI 10.1109/ACCT.2014.70.
- Matthew Morrison and Nagarajan Ranganathan, “Design of a Reversible ALU based on Novel Programmable Reversible Logic Gate Structures”, 2013 IEEE Computer Society Annual Symposium on VLSI.
- Lekshmi Viswanath and Ponni.M, “Design and Analysis of 16 Bit Reversible ALU”, ISSN: 2278-0661 Volume 1, Issue 1 (May-June 2012), PP 46-53.
- Akanksha Dixit and VinodKapse, “Arithmetic & Logic Unit (ALU) Design using Reversible Control Unit”, International Journal of Engineering and Innovative Technology (IJEIT) Volume 1, Issue 6, June 2012.
- Mr. Abhishek Gupta, Mr. UtsavMalviya and Prof. VinodKapse, “Design of Speed, Energy and Power Efficient Reversible Logic Based Vedic ALU for Digital Processors”, 2012 IEEE Computer Society Annual Symposium on VLSI.
- H. Thapliyal and N. Ranganathan, "A New Reversible Design of BCD Adder," To appear in Proc. Design Automation and Test in Europe (DATE), 2011.
- James Donald and Niraj K. Jha. Reversible logic synthesis with fredkin and peres gates. J. Emerg. Technol. Comput. Syst., 4:2:1–2:19, April 2008.
- Lenin Gopal, Nor Syahira Mohd Mahayadin and Adib Kabir Chowdhury, “Design and Synthesis of Reversible Arithmetic and Logic Unit (ALU)”, 2014 IEEE 2014 International Conference on Computer, Communication, and Control Technology (I4CT 2014), September 2 -4, 2014.
- Oleg Golubitsky, Sean M. Falconer, and Dmitri Maslov. Synthesis of the optimal 4-bit reversible circuits. In Proceedings of the 47th Design Automation Conference, DAC ’10, pages 653–656, New York, NY, USA, 2010. ACM.
- H. R. Bhagyalakshmi, M. K. Venkatesha, “An improved design of a multiplier using reversible logic gates”, International Journal of Engineering Science and Technology, Vol. 2(8), pp: 3838-3845, 2010.
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