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A Novel 7T SRAM Cell Layout Design with Low Average Power in Read and Write Cycles
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 157 - Number 3 |
| Year of Publication: 2017 |
| Authors: Abhishek Jain, Braj Bihari Soni |
10.5120/ijca2017912644
|
Abhishek Jain, Braj Bihari Soni . A Novel 7T SRAM Cell Layout Design with Low Average Power in Read and Write Cycles. International Journal of Computer Applications. 157, 3 ( Jan 2017), 13-17. DOI=10.5120/ijca2017912644
Abstract
The system memories requirement depends greatly on the nature of the applications which run on the system. Memory performance and capacity requirements are small for simple, low cost systems. In contrast, memory throughput can be the most critical requirement in complex, high performance systems. The following general types of memories can be used in systems such as Volatile and non-volatile memories. SRAM can be found in the cache memory of a computer or as a part of the RAM digital to analog converters on video cards. Static RAM is also used for high-speed registers, caches and small memory banks like a frame buffer on a display adapter. Several scientific and industrial subsystems, modern appliances, automotive electronics, electronic toys, mobile phones, synthesizers and digital cameras also use SRAM. It is also highly recommended for use in PCs, peripheral equipment, printers, LCD screens, hard disk buffers etc. Different transistor counts in used in SRAM architecture such as Bipolar junction transistors used in TTL and ECL which is very fast but consumes a lot of power and MOSFET used in CMOS which is used at low power and also very common today. This paper proposed to improve the stability of SRAM cell and also reduces the average power in standby mode. This paper presents a low average power based layout design of 7T SRAM [1] architecture.
References
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