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Reseach Article
A Result Analysis of ASIC Design of Reversible Multiplier Circuit
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 160 - Number 8 |
| Year of Publication: 2017 |
| Authors: Anand Dayal, Himanshu Shekhar |
10.5120/ijca2017913071
|
Anand Dayal, Himanshu Shekhar . A Result Analysis of ASIC Design of Reversible Multiplier Circuit. International Journal of Computer Applications. 160, 8 ( Feb 2017), 40-43. DOI=10.5120/ijca2017913071
Abstract
Reversible logic is very lots of in demand for the long term computing technologies as they are known to supply low power dissipation having its applications in Low Power, Quantum Computing, nanotechnology, and Optical Computing. during this paper, we have got given and implemented reversible Wallace signed multiplier circuit in ASIC through changed Baugh-Wooley approach using normal reversible logic gates/cells, based on complementary pass transistor logic and are valid with simulations, a layout vs. schematic check, and a design rule check.
References
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