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Design of 0. 13um CMOS Two Stage Low Noise Amplifier

International Journal of Computer Applications
© 2014 by IJCA Journal
Volume 100 - Number 15
Year of Publication: 2014
Samiksha Patre
Nilesh Bodane
Vinay Keswani

Samiksha Patre, Nilesh Bodane and Vinay Keswani. Article: Design of 0.13um CMOS Two Stage Low Noise Amplifier. International Journal of Computer Applications 100(15):17-20, August 2014. Full text available. BibTeX

	author = {Samiksha Patre and Nilesh Bodane and Vinay Keswani},
	title = {Article: Design of 0.13um CMOS Two Stage Low Noise Amplifier},
	journal = {International Journal of Computer Applications},
	year = {2014},
	volume = {100},
	number = {15},
	pages = {17-20},
	month = {August},
	note = {Full text available}


A Low Noise amplifier is one of the most commonly used components in analog and digital circuit designs. Low voltage and low power Low Noise amplifier design has become an increasingly interesting subject as many applications switch to portable battery powered operations. An electronic amplifier is an electronic device that increases the power of a signal. This design techniques is needed to allow amplifiers to maintain an acceptable level of performance when the supply voltages are decreased is immense for maintain low noise with high gain. The low-noise amplifier is a special type of electronic amplifier used to amplify very weak signals captured by an antenna. This paper presents a technique for substantially reducing the noise of a CMOS low noise amplifier implemented in the cascade inductive source degeneration topology. This 2. 4 GHz Two Stage CMOS 130nm RF Low Noise Amplifier is optimize for low noise at low current with very low power consumption. In this proposed design work the two stage cascade low noise amplifier is used to achieve noise < 2dB with the high gain up to > 28 dB, input return loss of >10 and output return loss of > -10 at 1. 3 supply voltage.


  • Thi Thu Nga Tran, Chim Chye Boon ,Manh Anh Do, and Kiat Seng Yeo A 2. 4 GHz ultra low-power high gain LNA utilizingx-match and capacitive feedback input network 978-1-61284-857-0/11@2011 IEEE
  • Hong-Sun Kim, Xiaopeng Li, and Mohammed Ismail, Fellow IEEE A 2. 4GHz CMOS Low Noise Amplifier using an Inter-sta. ge Matching Inductor 0-7803-5491-5/99/$10. 00 0 1999 IEEE
  • A. Pascht, Member, IEEE J. Fischer and M. Berroth, Member, IEEE A CMOS Low Noise Amplifier at 2. 4 GHz with Active Inductor Load 0-7803-7129-1/01/$10. 00 (C) 2001 IEEE
  • Meng Zhang 1, 2, 3, Zhiqun Li 1, 2, 3 A 2. 4 GHz Low Power Common-Gate Low Noise Amplifier for Wireless Sensor Network Applications 978-1-61284-307-0/11 ©2011 IEEE
  • T. T. N. Tran, C. C. Boon, M. A. Do and K. S. Yeo Ultra-low power series input resonance differential common gate LNA ELECTRONICS LETTERS 9th June 2011 Vol. 47 No. 12
  • François Belmas1, Frédéric Hameau1, Jean-Michel Fournier2 A 1. 3mW 20dB Gain Low Power Inductorless LNA with 4dB Noise Figure for 2. 45GHz ISM Band 978-1-4244-8292-4/11 ©2011 IEEE
  • Sambit Datta*, Kunal Datta*, Ashudeb Dutta#, Tarun Kanti Bhattacharyya* A Concurrent Low-Area Dual Band 0. 9/2. 4 GHz LNA in 0. 13?m RF CMOS Technology for Multi- Band Wireless Receiver 978-1-4244-7456-1/10 ©2010 IEEE
  • André Esteves, José Dores, Pedro Matos, Miguel A. Martins, Jorge R. Fernandes INESC-ID / Instituto Superior Técnico, TU Lisbon An ISM 2. 4 GHz Low-IF Receiver Frontend 978-1-4244-9474-3/11/$26. 00 ©2011 IEEE
  • R. J. Baker, "CMOS – Circuit Design, Layout and Simulation", 2nd edition, IEEE Press, 2005.
  • P. E. Allen and D. R. Holberg, "CMOS Analog Circuit Design", 2nd edition, Oxford University Press, 2002
  • B. Razavi, Design of analog CMOS integrated circuits, McGraw-Hill, 2000.
  • D. Johns and K. Martin, "Analog integrated circuit design," in John Wiley & Sons, New York, 1997.