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Vedic ALU using Area Optimised Urdhva Triyambakam Multiplier
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 103 - Number 14 |
| Year of Publication: 2014 |
| Authors: Anshul Khare, Ashish Raghuwanshi, Ruchi Gupta |
10.5120/18144-9380
|
Anshul Khare, Ashish Raghuwanshi, Ruchi Gupta . Vedic ALU using Area Optimised Urdhva Triyambakam Multiplier. International Journal of Computer Applications. 103, 14 ( October 2014), 28-31. DOI=10.5120/18144-9380
Abstract
Multiplication has some limits and to overcome these limitations a new approach has been describe and designed a Vedic multiplier with proposed unique addition structure, which is used to perform addition of partially generated products. To meet main concern 'area' and 'speed' we have came up with a need particular high speed ALU, the speed of ALU greatly depends upon the speed of multiplication unit used in it. There are numerous multiplication techniques exist now a days at algorithmic and structural level. It is been shown that Vedic multiplication is the fastest multiplication method but there are some other multiplication techniques which are batter then vedic multiplication in terms of chip area. This Proposed work is a unique architecture of 16 bit vedic with combination of 4 bit vedic multiplications and that 4 bit multiplication is been have developed with a unique addition structure. The observed results are been very good and optimised. Later on ALU module is been developed. The tool used for the designing is Xilinx XST and the target platform for validation is Vertex family vertex-4 FPGA, the preferred language is VHDL.
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