The week's pick
Reseach Article
Comparative Analysis of Metastability with D FLIP FLOP in CMOS Circuits
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 103 - Number 16 |
| Year of Publication: 2014 |
| Authors: Manisha Thakur, Puran Gaur, Braj Bihari Soni |
10.5120/18160-9383
|
Manisha Thakur, Puran Gaur, Braj Bihari Soni . Comparative Analysis of Metastability with D FLIP FLOP in CMOS Circuits. International Journal of Computer Applications. 103, 16 ( October 2014), 26-29. DOI=10.5120/18160-9383
Abstract
The appropriate choice of flip-flop topologies is of essential importance in the design of integrated circuits for CMOS VLSI high-performance and high-speed circuits. The understanding of the suitability of the flip-flops and select the best topology for a given application is important to meet the need of the design to meet low power and high performance circuit subject. This work shows a wide area comparison exist in D flip-flop, this provides a wide study of the topologies in terms of power dissipation, delay, and rise delay and fall delay time.
References
- David Rennie, DavidLi, Manoj Sachdev, Bharat L. Bhuva, Srikanth Jagannathan, ShiJieWen, and Richard Wong "Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS" IEEE Transactions On Circuits And Systems—I: Regular Papers, Vol. 59, No. 8, August 2012 pp no 1626.
- Haiqing Nan and Ken Choi "High Performance, Low Cost, and Robust Soft Error Tolerant Latch Designs for Nanoscale CMOS Technology" IEEE Transactions on Circuits and Systems—I: Regular Papers, Vol. 59, No. 7, July 2012 pp no 1445.
- David J. Rennie,and Manoj Sachdev "Novel Soft Error Robust Flip-Flops in 65nm CMOS" IEEE Transactions On Nuclear Science, Vol. 58, No. 5, October 2011 pp no. 2470.
- Pedro M. Figueiredo "Comparator Metastability in the Presence of Noise" IEEE Transactions, on circuits and Systems I: Regular Papers year 2012 pp no 1549.
- Mr Jun Zhou,Mr David J. Kinniment , Mr Charles E. Dike,and Mr Gordon Russell "On-Chip Measurement of Deep Metastability in Synchronizers" IEEE Journal Of Solid-State Circuits, Vol. 43, No. 2, in year 2008. pp no. 550.
- Keith A. Bowman, James W. Tschanz, Nam Sung Kim, Janice C. Lee, Chris B. Wilkerson, Shih-Lien L. Lu,Tanay Karnik, and Vivek K. De "Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance" IEEE Journal Of Solid-State Circuits, Vol. 44, No. 1, January 2009, pp no. 49.
- Ch. Daya Sagar, T. Krishna Moorthy, "Design of a Low Power Flip-Flop Using MTCMOS Technique" International Journal of Computer Applications & Information Technology Vol. 1, No. 1, July 2012.
- R. Uma, "Flip-Flop Circuit Families: Comparison of Layout and Topology for Low Power VLSI Circuits" International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www. ijera. com, Vol. 1, Issue 4, pp. 1971-1982.
- Kavita Mehta, Neha Arora, Prof. B. P. Singh, "Low Power Efficient D Flip Flop Circuit" International Symposium on Devices MEMS, Intelligent Systems & Communication (ISDMISC) 2011, Proceedings published by International Journal of Computer Applications (IJCA).
- Haiqing Nan and Ken Choi, "High Performance, Low Cost, and Robust Soft Error Tolerant Latch Designs for Nano scale CMOS Technology" IEEE Transactions on Circuits and Systems—I: Regular Papers, VOL. 59, No. 7, July 2012.
Index Terms
Keywords