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Mode Enabled Coprocessor for Precision Multipliers

by Dinesh Kumar, Girish Chander Lall
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 104 - Number 11
Year of Publication: 2014
Authors: Dinesh Kumar, Girish Chander Lall
10.5120/18246-9280

Dinesh Kumar, Girish Chander Lall . Mode Enabled Coprocessor for Precision Multipliers. International Journal of Computer Applications. 104, 11 ( October 2014), 14-17. DOI=10.5120/18246-9280

@article{ 10.5120/18246-9280,
author = { Dinesh Kumar, Girish Chander Lall },
title = { Mode Enabled Coprocessor for Precision Multipliers },
journal = { International Journal of Computer Applications },
issue_date = { October 2014 },
volume = { 104 },
number = { 11 },
month = { October },
year = { 2014 },
issn = { 0975-8887 },
pages = { 14-17 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume104/number11/18246-9280/ },
doi = { 10.5120/18246-9280 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:35:53.443894+05:30
%A Dinesh Kumar
%A Girish Chander Lall
%T Mode Enabled Coprocessor for Precision Multipliers
%J International Journal of Computer Applications
%@ 0975-8887
%V 104
%N 11
%P 14-17
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Multiplication and division are the two elementary operations essential for the core computing process or for the arithmetic operation. These two operations are also the most critical functions carried out by the processors, as the multiplication requires more number of steps for the computation, limiting the overall performance of the system, and the division has the highest latency among all arithmetic operations. Thus, high performance multiplication and division algorithms/ architectures, if available, will considerably improve the speeds of processing system. Consequently, the need for faster processing of arithmetic operations, is continuously driving major improvements in processor technologies, as well as the search for new arithmetic algorithms. In the present paper alternate design for single and double precision multiplier processor is presented.

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Index Terms

Computer Science
Information Sciences

Keywords

Processor FPGA Floating Point

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