The week's pick
Reseach Article
Low Power ALU Design considering PVT Variations
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 104 - Number 17 |
| Year of Publication: 2014 |
| Authors: D. Anitha, K. Manjunatha Chari, P. Satish Kumar |
10.5120/18300-9442
|
D. Anitha, K. Manjunatha Chari, P. Satish Kumar . Low Power ALU Design considering PVT Variations. International Journal of Computer Applications. 104, 17 ( October 2014), 19-23. DOI=10.5120/18300-9442
Abstract
ALU is one of the most important components in a microprocessor that carries out the arithmetic and logical operations. This paper highlights the techniques in designing a low power ALU in nanometer CMOS. Different 10 transistor full adders are compared and chosen the Full adder with least power dissipation to obtain low power and area efficient ALU. The power is reduced by 78% when compared to the existing ALU which is designed using XOR based Full adder. The proposed design does not compromise with the performance as the full adder delay is less. The functionality of the design remains the same despite the temperature and voltage variations. The power dissipation for different temperatures ranging from -50 0C to +50 0C has been observed. The ultimate goal is to design an ALU with the least number of transistors thereby decreasing the area and power consumption in the overall circuit that takes shape at the end.
References
- H. T. Bui, A. K. Al-Sheraidah, and Y. Wang, "Design and analysis of 10-transistor full adders using novel XOR-XNOR gates," in Proc. Int. Conf. Signal Processing 2000 (Wold Computer Congress), Beijing, China, Aug. 2000.
- P. Chandrakasan, S. Sheng, and R. W. Broderson, "Low-power CMOS digital design," IEEE J. Solid-State Circuits, vol. 27, pp. 473–483, Apr. 1992.
- R. Pedram and M. Pedram, Low Power Design Methodologies. Norwell, MA: Kluwer, 1996.
- N. Weste and K. Eshragian, Principles of CMOS VLSI Design: A Systems Perspective, Pearson/ Addison -Wesley Publishers, 2005.
- R. Zimmermannn and W. Fichtner, "Low-power logic styles: CMOS versus pass-transistor logic," IEEE J. Solid-State Circuits, vol. 32, pp. 1079–1090, July 1997. Y. Jiang, Y. Wang, and J. Wu, "Comprehensive Power Evaluation of Full Adders," Florida Atlantic Univ. , Boca Raton, Tech. Rep. , 2000.
- Meta-Software, HSPICE User's Manual Version H9002, 1992.
- Suzuki, M. et al. , "A 1. 5-ns 32-b CMOS ALU in double pass-transistor logic" IEEE Journal of Solid-State Circuits, Vol28, pp 1145-1151, 1993.
- Chandrakasan, A. , and Brodersen, Low Power Digital Design, Kluwer Academic Publishers, R. , 1995.
- R. Shalem, E. John, and L. K. John, "A novel low-power energy recovery full adder cell," in Proc. Great Lakes Symp. VLSI, Feb. 1999, pp. 380–383.
- Bellaouar, A. , and Elmasry, M. , Low-Power Digital VLSI Design: circuits and Systems Boston, Massachusetts: Kluwer Academic Publishers, 1995.
- L. Bisdounis, D. Gouvetas and O. Koufopavlou, "A comparative study of CMOS circuit design styles for lowpower high-speed VLSI circuits" Int. J. of Electronics, Vol. 84, No. 6, pp 599-613,1998. Anu Gupta, Design Explorations of VLSI Arithmetic Circuits, Ph. D. Thesis, BITS,Pilani, India, 2003.
- Sun,S. , and Tsui. P. , "Limitation of CMOS supply-voltage scaling by MOSFET threshold voltage" IEEE Journal of Solid-State Circuits, Vol. 30, pp 947-949, 1995.
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