CFP last date
20 May 2024
Call for Paper
June Edition
IJCA solicits high quality original research papers for the upcoming June edition of the journal. The last date of research paper submission is 20 May 2024

Submit your paper
Know more
The week's pick
Responsive image
Enhancing Privacy Preservation: Multi-Attribute Protection with P-Sensitive K-Anonymity

Twinkle Patel Kiran Amin
Random Articles
Reseach Article

Novel High Speed Low Power Binary Multiplier Designs using Reversible Logic Gates

by Naman Sharma, Upanshu Saraswat, Rajat Sachdeva
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 105 - Number 9
Year of Publication: 2014
Authors: Naman Sharma, Upanshu Saraswat, Rajat Sachdeva
10.5120/18403-9668

Naman Sharma, Upanshu Saraswat, Rajat Sachdeva . Novel High Speed Low Power Binary Multiplier Designs using Reversible Logic Gates. International Journal of Computer Applications. 105, 9 ( November 2014), 9-13. DOI=10.5120/18403-9668

@article{ 10.5120/18403-9668,
author = { Naman Sharma, Upanshu Saraswat, Rajat Sachdeva },
title = { Novel High Speed Low Power Binary Multiplier Designs using Reversible Logic Gates },
journal = { International Journal of Computer Applications },
issue_date = { November 2014 },
volume = { 105 },
number = { 9 },
month = { November },
year = { 2014 },
issn = { 0975-8887 },
pages = { 9-13 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume105/number9/18403-9668/ },
doi = { 10.5120/18403-9668 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:37:14.802043+05:30
%A Naman Sharma
%A Upanshu Saraswat
%A Rajat Sachdeva
%T Novel High Speed Low Power Binary Multiplier Designs using Reversible Logic Gates
%J International Journal of Computer Applications
%@ 0975-8887
%V 105
%N 9
%P 9-13
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Reversible logic is highly useful in nanotechnology, low power design and quantum computing. The paper proposes efficient MOS implementation for the basic reversible gates namely, Feynman, Toffoli, and Peres gates and employs the proposed circuits in the reversible binary multiplier design. It also juxtaposes the three proposed architectures to compare their properties and hence propose the most optimized form of the aforementioned multipliers.

References
  1. Laszlo B. Kish, Texas A&M University, Department of Electrical Engineering, College Station, TX 77843-3128, USA Received 16 July 2002; received in revised form 19 September 2002; accepted 19 September 2002, Communicated by C. R. Doering, "End of Moore's law: thermal (noise) death of integration in micro and nano electronics. "
  2. Trevor Pering, Tom Burd, and Robert Brodersen University of California Berkeley, Electronics Research Laboratory, "Dynamic Voltage Scaling and the: Design of a Low-Power Microprocessor System"
  3. C. H. Bennett, "Notes on the history of reversible computation," IBM J. Research and Development, vol. 32, pp. 16-23, January 1988.
  4. C. H. Bennett, "Logical reversibility of computation," IBM J. Research and Development, pp. 525-532, November 1973.
  5. R. W. Keyes and R. Landauer, "Minimal energy dissipation in logic," IBM J. Research and Development, pp. 152-157, March 1970.
  6. R. Landauer, "Irreversibility and heat generation in the computing process," IBM J. Research and Development, vol. 3, pp. 183-191, July 1961. '
  7. Jagadguru Swami, Sri Bharati Krisna, Tirthaji Maharaja, "Vedic Mathematics or Sixteen Simple Mathematical Formulae from the Veda, Delhi (1965)", Motilal Banarsidas, Varanasi, India, 1986.
  8. Ramalatha, M. Dayalan, K D Dharani, P Priya, and S Deoborah, "High Speed Energy Efficient ALU Design using Vedic Multiplication Techniques", International Conference on Advances in Computational Tools for Engineering Applications (ACTEA) IEEE, pp. 600-603, July 15-17, 2009.
  9. Pushpalata Verma, K. K. Mehta, "Implementation of an Efficient Multiplier based on Vedic Mathematics Using EDA Tool", International Journal of Engineering and Advanced Technology (IJEAT), ISSN: 2249 – 8958, Volume-1, Issue-5, June-2012.
  10. H. D. Tiwari, G. Gankhuyag, C. M. Kim, and Y. b. Cho, "Multiplier design based in ancient Indian Vedic Mathematics," in Proceeding IEEE International SoC Design Conference, Bussan, Nov. 24-25,2008,pp. 65-68.
  11. R. Feynman," Quantum Mechanical Computers", Optic News, Vol 11, pp 11-20 1985.
  12. T. Toffoli, "Reversible Computing", Tech memoMIT/LCS/TM-151, MIT Lab for Computer Science 1980.
  13. Fredkin E. Fredkin and T. Toffoli,, "Conservative Logic", Int'l J. Theoretical Physics Vol 21, pp. 219-253, 1982
  14. Peres, "Reversible Logic and Quantum Computers", Physical review A, 32:3266- 3276, 1985.
  15. X. Susan Christina, M. Sangeetha Justine, K. Rekha, U. Subha and R. Sumathi, ?Realization of BCD adder using Reversible Logic?, International Journal of Computer Theory and Engineering, Vol. 2, No. 3, June, 2010 1793-8201.
  16. N. Rajput, M. Sethi, P. Dobriyal, K. Sharma, G. Sharma, "A Novel, High Performance and Power Efficient Implementation of 8x8 Multiplier Unit using MT-CMOS Technique", IEEE Explore, 2013.
  17. Padmanabhan Pillai and Kang G. Shin, "Real-Time Dynamic Voltage Scaling for Low-Power Embedded Operating Systems", Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science The University of Michigan Ann Arbor, MI 48109-2122, U. S. A.
  18. Asher Pers, "Reversible logic and quantum computers", The American Physical Society
Index Terms

Computer Science
Information Sciences

Keywords

Reversible logic Vedic multiplier Quantum computing.

Powered by PhDFocusTM