The week's pick
Reseach Article
Design and Performance Evaluation of High Speed MAC Unit with Parallel Pipeline Technology
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 106 - Number 4 |
| Year of Publication: 2014 |
| Authors: Y. Narasimha Rao, Gsvp Raju, Penmetsa V Krishna Raja |
10.5120/18506-9575
|
Y. Narasimha Rao, Gsvp Raju, Penmetsa V Krishna Raja . Design and Performance Evaluation of High Speed MAC Unit with Parallel Pipeline Technology. International Journal of Computer Applications. 106, 4 ( November 2014), 7-10. DOI=10.5120/18506-9575
Abstract
In recent days advanced digital process demands more sophisticated parameters such as throughput, power and area. It is very difficult to maintain high throughput while maintaining optimum power consumption and cell area. In most of the digital systems multipliers are deciding their performance in terms of above parameters. In the present work high speed Vedic multipliers are designed with pipeline technology. As the MAC speed is decided by Vedic Multiplier, in the present paper Multiplier and Accumulator (MAC) is designed with two way pipeline technology to meet high throughput. Vedic Multipliers are used in designing MAC unit as they are fast multipliers and further enhancing the data speed. The MAC is implemented with Cadence Encounter(R) RTL Compiler.
References
- Booth, A. D. , "A signed binary multiplicationtechnique," Quarterly Journal of Mechanics andApplied Mathematics, vol. 4, pt. 2, pp. 236– 240,1951.
- Jagadguru Swami Sri Bharath, KrsnaTirathji,"Vedic Mathematics or Sixteen Simple Sutras FromThe Vedas", MotilalBanarsidas,Varanasi(India),1986.
- PratikshaRai et al. , "Design of Floating PointMultiplier Using Vedic Aphorisms", IJETT, Vol11, No 3, May 2014, pp123-126.
- Jagadguru Swami Sri BharatiKrsnaTilihjiMotilal Maharaja. (1986), VedicMathematics, et al. "Design And ImplementationOf Efficient Multiplier Using Vedic Mathematics,proc. Of Int. conf. on Advanced in Recent Technologies in Communication and computing",proc. Of Int. conf. on Advanced in RecentTechnologies in Communication and computing,2011.
- Y. Narasimharao et al. , "Design of high speed Vedic multiplier withpipeline technology", JATIT, VOL 67, Issue no 3, September 2014.
- V. K. Karthik et al. , "Design of Multiply and Accumulate Unit using Vedic Multiplication Techniques", IJSER, Vol 4 no6, june 2013. pp756-760.
- Y. N. Rao et al. , "Simple and Efficient Low Power Parallel Pipelined Vedic Multiplier", Vol 9, NO 21, IJAER, pp9765-9774.
- Anveshkumar et al. , "Low Power ALU Design by Ancient Mathematics", doi: 978-1-4244-5586-7/10/$26. 00, IEEE, © 2010, pp862-865.
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