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Design of Low Power 16-Bit Novel Carry Select Adder using 0.18um Technology
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 110 - Number 7 |
| Year of Publication: 2015 |
| Authors: M. Lavanya, D. Nageshwar Rao, K. Rama Krishna |
10.5120/19330-0863
|
M. Lavanya, D. Nageshwar Rao, K. Rama Krishna . Design of Low Power 16-Bit Novel Carry Select Adder using 0.18um Technology. International Journal of Computer Applications. 110, 7 ( January 2015), 22-25. DOI=10.5120/19330-0863
Abstract
In this paper, a Novel 16-bit carry select adder (CSLA) is proposed to perform fast arithmetic operation in many data-processing processors. The proposed design combines the modified 16-bit carry select adder and a carry select adder by sharing the common Boolean Logic term. The area and power of the Novel 16-bit carry select adder significantly reduces when compared with modified 16-bit carry select adder[2]. This work evaluates the performance of the proposed design in terms of total number of gates, area, delay and power using Cadence Virtuoso gpdk 180nm technology. In this proposed design the transistor count of a 16-bit carry select adder reduced from 470 to 432 gates which reduce the area by 13. 64µm2. Moreover, the power consumption has reduced from 9. 206n watts to 6. 648n watts. The delay of the Novel 16-bit carry select adder increased by 29. 626*10-18s. The result analysis shows that the Novel 16-bit CSLA is better than modified and regular 16-bit CSLA [1].
References
- M. Lavanya. , "Gate count comparison of Different 16-bit Carry Select Adders," International Journal of Advanced Research in Electrical,Electronics and Instrumentation Engineering,Vol. 3, issue 7, pp. 10846-10853, July 2014.
- Rajesh, A. ; Madhumalini, M. , "An efficient structure of carry select adder," Green Computing Communication and Electrical Engineering (ICGCCEE), 2014 International Conference on , vol. , no. , pp. 1,5, 6-8 March 2014
- Mohanty, B. K. ; Patel, S. K. , "Area-Delay-Power Efficient Carry-Select Adder," Circuits and Systems II: Express Briefs, IEEE Transactions on , vol. 61, no. 6, pp. 418,422, June 2014
- B. Ramkumar and Harish M Kittur. , " Low-Power and Area-Efficient Carry Select Adder," IEEE transactions on very large scale integration (VLSI) systems, vol. 20, no. 2, February 2012.
- I-Chyn Wey, Cheng-Chen Ho, Yi-Sheng Lin, and Chien-Chang Peng, "An Area-Efficient Carry Select Adder Design by Sharing the Common Boolean Logic Term," International Multi Conference of Engineers and Computer Scientists 2012 volume II, March 14-16 2012.
- J. M. Rabaey, Digital Integrated Circuits—A Design Perspective. Upper Saddle River, NJ: Prentice-Hall, 2001.
- Cadence, "Encounter user guide," Version 6. 2. 4, March 2008
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