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Reseach Article

Reduction of Leakage Power in Half- Subtractor using AVL Technique based on 45nm CMOS Technology

by Anand Singh Narwariya, Shyam Akashe
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 111 - Number 1
Year of Publication: 2015
Authors: Anand Singh Narwariya, Shyam Akashe
10.5120/19504-1102

Anand Singh Narwariya, Shyam Akashe . Reduction of Leakage Power in Half- Subtractor using AVL Technique based on 45nm CMOS Technology. International Journal of Computer Applications. 111, 1 ( February 2015), 31-35. DOI=10.5120/19504-1102

@article{ 10.5120/19504-1102,
author = { Anand Singh Narwariya, Shyam Akashe },
title = { Reduction of Leakage Power in Half- Subtractor using AVL Technique based on 45nm CMOS Technology },
journal = { International Journal of Computer Applications },
issue_date = { February 2015 },
volume = { 111 },
number = { 1 },
month = { February },
year = { 2015 },
issn = { 0975-8887 },
pages = { 31-35 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume111/number1/19504-1102/ },
doi = { 10.5120/19504-1102 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:46:44.677859+05:30
%A Anand Singh Narwariya
%A Shyam Akashe
%T Reduction of Leakage Power in Half- Subtractor using AVL Technique based on 45nm CMOS Technology
%J International Journal of Computer Applications
%@ 0975-8887
%V 111
%N 1
%P 31-35
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The analytical paper of arithmetic circuits plays an important role in designing of any VLSI system. Subtractor is one of them. Half Subtractor is being designed using Adaptive Voltage Level (AVL) techniques. This design consumed less power as compare to conventional design. We can reduce the value of total power dissipation by applying the AVLG (adaptive voltage level at ground) technology in which the ground potential is raised and AVLS (adaptive voltage level at supply) in which supply potential is increased. This paper represents how to control power using AVL techniques. The AVL technique based Half Subtractor compared to conventional design that based on power consumption, propagation delay, speed and layout area is more preferred. Power consumption of the projected cell is measured and compared. The result shows that there is a significant reduction in power consumption for this proposed cell with the AVL technique. This styal is much useful in designing the system that consumed less power. The circuit is simulated on Cadence tools in 45 nanometer CMOS technology.

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Index Terms

Computer Science
Information Sciences

Keywords

Half–Subtractor AVLG techniques AVLS techniques Low Power and High Speed