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Space Optimized Multiplier Architecture for Embedded Cryptoprocessor
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 113 - Number 14 |
| Year of Publication: 2015 |
| Authors: Sunil Devidas Bobade, Vijay R.mankar |
10.5120/19897-1982
|
Sunil Devidas Bobade, Vijay R.mankar . Space Optimized Multiplier Architecture for Embedded Cryptoprocessor. International Journal of Computer Applications. 113, 14 ( March 2015), 26-32. DOI=10.5120/19897-1982
Abstract
The finite field modular multiplier is the most critical component in the elliptic curve crypto processor (ECCP) consuming the maximum chip area and contributing the most to the device latency. Modular multiplication, point multiplication, point doubling are few of the critical activities to be carried out by multiplier in ECC algorithm, and should be managed without compromising on security and without burdening space and time complexities. Since the area complexity of the Crypto processor is mainly based on the Modular Multiplier incorporated within the ECC processor, the major contribution of this work includes the replacement of traditional Karatsuba multiplier with the proposed space optimized multiplier inside the processor The complete modular multiplier and the cryptoprocessor module is synthesized and simulated using Xilinx ISE Design suite 14. 4 software. Experimental investigation show an improvement in area efficiency of cryptoprocessor, since proposed scheme occupies relatively reduced percentage area of FPGA as compared to the one using traditional Karatsuba multiplier.
References
- Blake, I. F. , Seroussi, G. , and N. P. Elliptic curves in cryptography. Cambridge University Press, New York, NY, USA, 1999.
- C. Paar. Efficient VLSI Architectures for Bit Parallel Computation in Galois Fields. PhD thesis, University at GH Essen, VDI Verlag, 1994.
- B. Sunar and C¸. K. Koc¸. Mastrovito multiplier for all trinomials. IEEE Transactions on Computers, 48(5):522–527, May 1999.
- C. Paar. A new architecture for a parallel finite field multiplier with low complexity based on composite fields. IEEE Transactions on Computers, 45(7):856– 861, July 1996.
- Ashkan Hosseinzadeh Namin, Huapeng Wu, and Majid Ahmadi, "A word-level finite field multiplier using normal basis", IEEE Transactions on computers, Vol. 60, No. 6, pp: 890- 895, Jun. 2011
- Hossein Mahdizadeh and Massoud Masoumi, "Novel architecture for efficient FPGA implementation of elliptic curve cryptographic processor over GF(2163)", IEEE Transactions on very large scale integration (vlsi) systems, Vol. 21, NO. 12, pp: 2330- 2333, Dec. 2013
- Y. I. Cho, N. S. Chang, C. H. Kim, Y. -H. Park, and S. Hong, "New Bit Parallel Multiplier With Low Space Complexity for All Irreducible Trinomials Over," IEEE Trans. VLSI Syst. , vol. 20, no. 10, pp. 1903–1908, Oct. 2012.
- M. Morales-Sandoval, C. Feregrino-Uribe, and P. Kitsos, "Bit-serial and digit-serial GF (2m) Montgomery multipliers using linear feedbackshift registers," Computers Digital Techniques, IET, vol. 5, no. 2, pp. 86–94, Mar. 2011.
- A. Hariri and A. Reyhani-Masoleh, "Digit-Serial Structures for the Shifted Polynomial Basis Multiplication over Binary Extension Fields," WAIFI 2008, LNCS 5130. Springer, pp. 103–116, Jul. 2008.
- J. Lin, "Low-latency Digit-serial Systolic Double Basis Multiplier over GF (2 m ) using Subquadratic Toeplitz Matrix-vector Product Approach," IEEE Trans. Comput. , vol. PP, no. 99, p. 1, 2012
- Roy. S. S, Rebeiro,C and Mukhopadhyay. D, "Theoretical modeling of elliptic curve scalar multiplier on LUT-based FPGAs for area and speed", IEEE Transactions on Very Large Scale Integration (VLSI) systems, Vol. 21, No. 5, May 2013.
- Hossein Mahdizadeh and Massoud Masoumi, "A novel architecture for efficient FPGA implementation of elliptic curve cryptographic processor over GF(2163)",IEEE Transactions on very large scale integration systems, Vol. 21, No. 12, Dec 2013
- Kazuo Sakiyama, Miroslav Knezevica, Junfeng Fana, , Bart Preneela, and Ingrid Verbauwhedea, "Tripartite modular multiplication", Integration, the VLSI Journal, Vol. 44, No. 4, pp: 259–269, September 2011.
- Gregory C. Ahlquist, Brent E. Nelson, and Michael Rice, "Optimal Finite Field Multipliers for FPGAs," in FPL '99: Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications, London, UK, 1999, pp. 51–60, Springer-Verlag.
- Ç. K. Koç and B. Sunar, "An Efficient Optimal Normal Basis Type II Multiplier," IEEE Trans. Comput. , vol. 50, no. 1, pp. 83–87, 2001.
- Y. I. Cho, N. S. Chang, C. H. Kim, Y. -H. Park, and S. Hong, "New Bit Parallel Multiplier With Low Space Complexity for All Irreducible Trinomials Over," IEEE Trans. VLSI Syst. , vol. 20, no. 10, pp. 1903–1908, Oct. 2012.
- M. Morales-Sandoval, C. Feregrino-Uribe, and P. Kitsos, "Bit-serial and digit-serial GF (2m) Montgomery multipliers using linear feedbackshift registers," Computers Digital Techniques, IET, vol. 5, no. 2, pp. 86–94, Mar. 2011
- Reza Azarderakhsh and Koray Karabina,"A new double point multiplication algorithm and its application to binary elliptic curves with endomorphisms", IEEE Transactions on Computers, No. 99, May 2013.
- A. Kaleel Rahuman and G. Athisha, "Reconfigurable Architecture for Elliptic Curve Cryptography Using FPGA", Hindawi Publishing Corporation Mathematical Problems in Engineering, 2013
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