CFP last date
22 July 2024
Reseach Article

Performance Analysis of Magnitude Comparator using Different Design Techniques

by Meena Aggarwal, Rajesh Mehra
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 115 - Number 14
Year of Publication: 2015
Authors: Meena Aggarwal, Rajesh Mehra

Meena Aggarwal, Rajesh Mehra . Performance Analysis of Magnitude Comparator using Different Design Techniques. International Journal of Computer Applications. 115, 14 ( April 2015), 12-15. DOI=10.5120/20218-2496

@article{ 10.5120/20218-2496,
author = { Meena Aggarwal, Rajesh Mehra },
title = { Performance Analysis of Magnitude Comparator using Different Design Techniques },
journal = { International Journal of Computer Applications },
issue_date = { April 2015 },
volume = { 115 },
number = { 14 },
month = { April },
year = { 2015 },
issn = { 0975-8887 },
pages = { 12-15 },
numpages = {9},
url = { },
doi = { 10.5120/20218-2496 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
%0 Journal Article
%1 2024-02-06T22:54:48.012084+05:30
%A Meena Aggarwal
%A Rajesh Mehra
%T Performance Analysis of Magnitude Comparator using Different Design Techniques
%J International Journal of Computer Applications
%@ 0975-8887
%V 115
%N 14
%P 12-15
%D 2015
%I Foundation of Computer Science (FCS), NY, USA

Comparators are a basic design module and element in modern digital VLSI design, digital signal processors and data processing application-specific integrated circuits. This paper comprises of design of three different comparators for 2, 4 and 8 bit magnitude comparison. The above said designs are prepared using two different design approaches: Weighted Logic and PTL . The above two design approaches are designed in a way to endow with good quality performance. . The performance of these three different comparators in the two design styles has been compared in terms of area and power consumption which are the important parameters that are considered while designing any digital circuit. The schematic are designed and simulated for its behavior using DSCH-3. 1. The layout of simulated circuits are created using Verilog based netlist file which is then simulated in Microwind 3. 1 to analyze the performance of comparators for the two design styles at 45nm and 32 nm CMOS technology.

  1. Morgenshtein, A. , Fish A. , Wagner, I. A. , "Gate- diffusion input (GDI): A Power Efficient Method for Digital Combinational circuits," IEEE Transaction on Very Large Scale Integration (VLSI) Systems, Vol. 10 , No. 5 , pp. 566 - 581 , 2002.
  2. Anjuli and Satyajit Anand," 2- Bit Magnitude Comparator design using different logic styles," International Journal of Engineering Science Invention , Vol. 2 ,No. 1, pp. 13-24, 2013.
  3. Vandana Choudhary, Rajesh Mehra, " 2-bit CMOS compartor by Hybridizing PTL and Pseudo logic," International Journal of Recent Technology and Engineering, Vol. 2, No. 2, pp. 29-31,2013.
  4. Ahmed Magdy and Mohab Anis, " High Performance Energy-Efficient Arithmetic Circuits using Weighted Logic," 8th IEEE International New Circuits and Systems conference, pp. 57-60, 2010.
  5. N. Weste and D. Harris, CMOS VLSI Design: A Circuits and System Perspective, 3rd ed. Reading, MA, USA: Addison-Wesley , May 2004.
  6. H. -. M. Lam and C. -Y. Tsui, "A MUX-based high-performance single-cycle CMOS comparator," IEEE Transaction on Circuits System II, Vol. 54, No. 7, pp. 591-595, 2007.
  7. Chiou-Kou Tung; Yu-Cherng Hung; Shao-Hui Shieh; Guo-Shing Huang, " A Low -Power High-speed Hybrid CMOS Full Adder For Embedded System," IEEE Transaction on Design and Diagnostics of Electronic Circuits and Systems, Vol. 13, No. 6, pp. 1- 4, 2007.
  8. Geetanjali Sharma, Uma Nirmal, Yogesh Mishra, "A Low Power 8-bit Magnitude Comparator With Small Transistor Count using Hybrid PTL/CMOS Logic," International Journal of Computational Engineering & Management, Vol. 2, No. 2, pp. 110-115, 2011.
  9. Manoj Kumar, Sandeep K. Arya1, and Sujata Pandey, " Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate," International Journal of VLSI design & Communication Systems, Vol. 2, No. 4, pp. 47-59, 2011.
  10. Anjali Sharma, Richa Singh, Rajesh Mehra, Member, IEEE, "Low Power TG Full Adder Design Using CMOS Nano Technology," IEEE International Conference on Parallel, Distributed and Grid Computing, pp. 210-213, 2012.
  11. Subodh Wairya, Rajendra Kumar Nagaria ,Sudarshan Tiwari, "Comparative Performance Analysis of XOR/XNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design," International Journal Of VLSI Design & Communication System,Vol. 3, No. 2, pp. 221-242, 2012.
  12. Vandana Dubey, O. P. Singh, G. R. Mishra, " Design and Implementation of a Two-Bit Binary Comparator Using Reversible Logic," International Journal of Scientific and Research Publications, Vol. 2, No. 7, pp. 1-4, 2012.
  13. Laxmi Kumre, Ajay Somkuwar, Ganga Agnihotri, "Design of Low Power 8 bit GDI Magnitude Comparator," International Journal of Emerging Technologies in Computational and Applied Sciences (IJETCAS),Vol. 4, pp. 102-108, 2013.
  14. Anjali Sharma, Richa Singh, Pankaj Kajla , " Area Efficient 1-bit comparator Design by using Hybridized Full Adder Module based on PTL and GDI logic," International Journal of Computer Applications, Vol. 82, No. 10, pp. 5-13, 2013.
  15. Anjali Sharma, Rajesh Mehra, "Area and Power Efficient CMOS Adder Design by Hybridizing PTL and GDI Technique," International Journal of Computer Applications, Vol. 66, No. 4, pp. 15-22, 2013.
  16. Arkadiy Morgenshtein ,Viacheslav Yuzhaninov, Alexey Kovshilovsky, Alexander Fish, "Full-swing Gate Diffusion input logic," Integration, the VLSI Journal, Vol. 47, pp. 62-70, 2014.
  17. Pooja Singh , Rajesh Mehra, "Design Analysis of XOR Gates Using CMOS & Pass Transistor Logic," National Student Conference on Advances in Electrical & Information Communication Technology, AEICT-2014, pp. 264-267, 2014.
  18. K. Rajasekhar, P. Sowjanya, V. Umakiranmai, R. Harish, M. Krishna , "Design and Analysis of comparator using different logic style of full adder," International journal of Engineering Research and Applications,Vol. 4, No. 4, pp . 389-393, 2014.
  19. Sharma. A, Sharma. P, "Area and power efficient 4-bit comparator design by using 1-bit full adder module," IEEE conference on Parallel, Distributed and Grid Computing, pp. 1-6, 2014.
  20. Microwind and DSCH version 3. 1, User's Manual, Copyright 1997-2007, Microwind INSA France.
Index Terms

Computer Science
Information Sciences


ALU Comparators CMOS style Digital Arithmetic Full Adder module PTL logic GDI technique.