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Performance Analysis of Magnitude Comparator using Different Design Techniques
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 115 - Number 14 |
| Year of Publication: 2015 |
| Authors: Meena Aggarwal, Rajesh Mehra |
10.5120/20218-2496
|
Meena Aggarwal, Rajesh Mehra . Performance Analysis of Magnitude Comparator using Different Design Techniques. International Journal of Computer Applications. 115, 14 ( April 2015), 12-15. DOI=10.5120/20218-2496
Abstract
Comparators are a basic design module and element in modern digital VLSI design, digital signal processors and data processing application-specific integrated circuits. This paper comprises of design of three different comparators for 2, 4 and 8 bit magnitude comparison. The above said designs are prepared using two different design approaches: Weighted Logic and PTL . The above two design approaches are designed in a way to endow with good quality performance. . The performance of these three different comparators in the two design styles has been compared in terms of area and power consumption which are the important parameters that are considered while designing any digital circuit. The schematic are designed and simulated for its behavior using DSCH-3. 1. The layout of simulated circuits are created using Verilog based netlist file which is then simulated in Microwind 3. 1 to analyze the performance of comparators for the two design styles at 45nm and 32 nm CMOS technology.
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